Lines Matching +full:0 +full:x23000

32 	{ 249600000, 2000000000, 0 },
37 	.l = 0x20,
38 	.alpha = 0x0,
39 	.config_ctl_val = 0x20485699,
40 	.config_ctl_hi_val = 0x00002261,
41 	.config_ctl_hi1_val = 0xB2923BBC,
42 	.user_ctl_val = 0x00005100,
43 	.user_ctl_hi_val = 0x00050805,
44 	.user_ctl_hi1_val = 0x00000000,
48 	.offset = 0x1000,
56 				.index = 0,
65 	{ 0x5, 5 },
70 	.offset = 0x1000,
88 	.reg = 0x1054,
89 	.shift = 0,
104 	{ P_BI_TCXO, 0 },
109 	{ .index = 0 },
114 	{ P_BI_TCXO, 0 },
126 	F(19200000, P_BI_TCXO, 1, 0, 0),
127 	F(51200000, P_LPASS_CORE_CC_DIG_PLL_OUT_MAIN_DIV_CLK_SRC, 6, 0, 0),
128 	F(102400000, P_LPASS_CORE_CC_DIG_PLL_OUT_MAIN_DIV_CLK_SRC, 3, 0, 0),
129 	F(204800000, P_LPASS_CORE_CC_DIG_PLL_OUT_MAIN, 3, 0, 0),
134 	.cmd_rcgr = 0x1d000,
157 	F(8192000, P_LPASS_CORE_CC_DIG_PLL_OUT_ODD, 15, 0, 0),
158 	F(9600000, P_BI_TCXO, 2, 0, 0),
159 	F(12288000, P_LPASS_CORE_CC_DIG_PLL_OUT_ODD, 10, 0, 0),
160 	F(19200000, P_BI_TCXO, 1, 0, 0),
161 	F(24576000, P_LPASS_CORE_CC_DIG_PLL_OUT_ODD, 5, 0, 0),
166 	.cmd_rcgr = 0x10000,
180 	.cmd_rcgr = 0x11000,
194 	.cmd_rcgr = 0x20000,
208 	.halt_reg = 0x1f000,
210 	.hwcg_reg = 0x1f000,
213 		.enable_reg = 0x1f000,
214 		.enable_mask = BIT(0),
228 	.halt_reg = 0x10018,
231 		.enable_reg = 0x10018,
232 		.enable_mask = BIT(0),
246 	.halt_reg = 0x11018,
249 		.enable_reg = 0x11018,
250 		.enable_mask = BIT(0),
264 	.halt_reg = 0x1e000,
267 		.enable_reg = 0x1e000,
268 		.enable_mask = BIT(0),
282 	.halt_reg = 0x1e004,
285 		.enable_reg = 0x1e004,
286 		.enable_mask = BIT(0),
300 	.halt_reg = 0x20014,
303 		.enable_reg = 0x20014,
304 		.enable_mask = BIT(0),
318 	.halt_reg = 0x23000,
320 	.hwcg_reg = 0x23000,
323 		.enable_reg = 0x23000,
324 		.enable_mask = BIT(0),
338 	.gdscr = 0x0,
399 	lpass_core_cc_sc7280_regmap_config.max_register = 0x4f004;  in lpass_core_cc_sc7280_probe()
424 	lpass_core_cc_sc7280_regmap_config.max_register = 0x24;  in lpass_hm_core_probe()
427 	return qcom_cc_probe_by_index(pdev, 0, desc);  in lpass_hm_core_probe()