Lines Matching +full:0 +full:x48
29 .l_reg = 0x4,
30 .m_reg = 0x8,
31 .n_reg = 0xc,
32 .config_reg = 0x14,
33 .mode_reg = 0x0,
34 .status_reg = 0x18,
50 { P_CXO, 0 },
71 { 27000000, P_CXO, 1, 0, 0 },
87 { 27000000, P_CXO, 1, 0, 0 },
92 .ns_reg = 0x48,
93 .md_reg = 0x4c,
107 .src_sel_shift = 0,
112 .enable_reg = 0x48,
129 .halt_reg = 0x50,
133 .enable_reg = 0x48,
146 .reg = 0x48,
150 .enable_reg = 0x48,
162 .halt_reg = 0x50,
163 .halt_bit = 0,
166 .enable_reg = 0x48,
179 .reg = 0x48,
213 .src_sel_shift = 0, \
267 .halt_bit = 0, \
302 CLK_AIF_OSR_DIV(codec_i2s_mic, 0x60, 0x64, 0x68);
303 CLK_AIF_OSR_DIV(spare_i2s_mic, 0x78, 0x7c, 0x80);
304 CLK_AIF_OSR_DIV(codec_i2s_spkr, 0x6c, 0x70, 0x74);
305 CLK_AIF_OSR_DIV(spare_i2s_spkr, 0x84, 0x88, 0x8c);
320 { 27000000, P_CXO, 1, 0, 0 },
337 { 27000000, P_CXO, 1, 0, 0 },
342 .ns_reg = 0x54,
343 .md_reg = 0x58,
357 .src_sel_shift = 0,
362 .enable_reg = 0x54,
375 .halt_reg = 0x5c,
376 .halt_bit = 0,
379 .enable_reg = 0x54,
392 .reg = 0x54,
410 .ns_reg = 0xcc,
411 .md_reg = 0xd0,
425 .src_sel_shift = 0,
430 .enable_reg = 0xcc,
447 .halt_reg = 0xd4,
448 .halt_bit = 0,
451 .enable_reg = 0xcc,
464 .halt_reg = 0xd4,
468 .enable_reg = 0xcc,
519 .max_register = 0xfc,
545 regmap_read(regmap, 0x4, &val); in lcc_mdm9615_probe()
546 if (val == 0x12) { in lcc_mdm9615_probe()
556 regmap_write(regmap, 0xc4, 0x1); in lcc_mdm9615_probe()