Lines Matching +full:0 +full:x1020
36 .halt_reg = 0x1020,
38 .enable_reg = 0x1020,
39 .enable_mask = BIT(0),
53 { 249600000, 2000000000, 0 },
58 { 0x0, 1 },
59 { 0x1, 2 },
60 { 0x3, 4 },
61 { 0x7, 8 },
66 .offset = 0x0,
79 .offset = 0x0,
95 { P_XO, 0 },
105 { P_XO, 0 },
115 F(19200000, P_XO, 1, 0, 0),
116 F(50000000, P_GPLL0, 12, 0, 0),
121 .cmd_rcgr = 0x1030,
139 .cmd_rcgr = 0x1070,
153 F(19200000, P_XO, 1, 0, 0),
158 .cmd_rcgr = 0x10b0,
171 F(19200000, P_XO, 1, 0, 0),
172 F(40000000, P_GPLL0, 15, 0, 0),
173 F(200000000, P_GPLL0, 3, 0, 0),
174 F(300000000, P_GPLL0, 2, 0, 0),
179 .cmd_rcgr = 0x1100,
192 .halt_reg = 0x1054,
194 .enable_reg = 0x1054,
195 .enable_mask = BIT(0),
207 .halt_reg = 0x1098,
209 .enable_reg = 0x1098,
210 .enable_mask = BIT(0),
222 .halt_reg = 0x10d0,
224 .enable_reg = 0x10d0,
225 .enable_mask = BIT(0),
237 .halt_reg = 0x1124,
239 .enable_reg = 0x1124,
240 .enable_mask = BIT(0),
251 .gdscr = 0x1004,
252 .gds_hw_ctrl = 0x1008,
261 .gdscr = 0x1094,
262 .clamp_io_ctrl = 0x130,
265 .cxcs = (unsigned int []){ 0x1098 },
295 [GPU_CX_BCR] = { 0x1000 },
296 [RBCPR_BCR] = { 0x1050 },
297 [GPU_GX_BCR] = { 0x1090 },
298 [GPU_ISENSE_BCR] = { 0x1120 },
305 .max_register = 0x9000,
336 regmap_write_bits(regmap, gfx3d_clk.clkr.enable_reg, BIT(0), BIT(0)); in gpucc_msm8998_probe()