Lines Matching +full:0 +full:x3b00
33 .l_reg = 0x30c4,
34 .m_reg = 0x30c8,
35 .n_reg = 0x30cc,
36 .config_reg = 0x30d4,
37 .mode_reg = 0x30c0,
38 .status_reg = 0x30d8,
49 .enable_reg = 0x34c0,
50 .enable_mask = BIT(0),
62 .l_reg = 0x3164,
63 .m_reg = 0x3168,
64 .n_reg = 0x316c,
65 .config_reg = 0x3174,
66 .mode_reg = 0x3160,
67 .status_reg = 0x3178,
78 .enable_reg = 0x34c0,
89 .l_reg = 0x3144,
90 .m_reg = 0x3148,
91 .n_reg = 0x314c,
92 .config_reg = 0x3154,
93 .mode_reg = 0x3140,
94 .status_reg = 0x3158,
105 .enable_reg = 0x34c0,
118 .mode_reg = 0x3200,
119 .l_reg = 0x3208,
120 .m_reg = 0x320c,
121 .n_reg = 0x3210,
122 .config_reg = 0x3204,
123 .status_reg = 0x321c,
124 .config_val = 0x7845c665,
125 .droop_reg = 0x3214,
126 .droop_val = 0x0108c000,
144 .mode_reg = 0x3240,
145 .l_reg = 0x3248,
146 .m_reg = 0x324c,
147 .n_reg = 0x3250,
148 .config_reg = 0x3244,
149 .status_reg = 0x325c,
150 .config_val = 0x7845c665,
151 .droop_reg = 0x3314,
152 .droop_val = 0x0108c000,
170 .mode_reg = 0x3300,
171 .l_reg = 0x3308,
172 .m_reg = 0x330c,
173 .n_reg = 0x3310,
174 .config_reg = 0x3304,
175 .status_reg = 0x331c,
176 .config_val = 0x7845c665,
177 .droop_reg = 0x3314,
178 .droop_val = 0x0108c000,
196 .l_reg = 0x31c4,
197 .m_reg = 0x31c8,
198 .n_reg = 0x31cc,
199 .config_reg = 0x31d4,
200 .mode_reg = 0x31c0,
201 .status_reg = 0x31d8,
212 .enable_reg = 0x34c0,
234 NSS_PLL_RATE(550000000, 44, 0, 1, 0x01495625),
235 NSS_PLL_RATE(600000000, 48, 0, 1, 0x01495625),
236 NSS_PLL_RATE(733000000, 58, 16, 25, 0x014b5625),
237 NSS_PLL_RATE(800000000, 64, 0, 1, 0x01495625),
241 .l_reg = 0x31a4,
242 .m_reg = 0x31a8,
243 .n_reg = 0x31ac,
244 .config_reg = 0x31b4,
245 .mode_reg = 0x31a0,
246 .status_reg = 0x31b8,
260 .l_reg = 0x3184,
261 .m_reg = 0x3188,
262 .n_reg = 0x318c,
263 .config_reg = 0x3194,
264 .mode_reg = 0x3180,
265 .status_reg = 0x3198,
289 { P_PXO, 0 },
299 { P_PXO, 0 },
311 { P_PXO, 0 },
316 { P_PXO, 0 },
326 { P_PXO, 0 },
338 { P_PXO, 0 },
354 { P_PXO, 0 },
373 { P_PXO, 0 },
410 .ns_reg = 0x29d4,
411 .md_reg = 0x29d0,
425 .src_sel_shift = 0,
430 .enable_reg = 0x29d4,
443 .halt_reg = 0x2fcc,
446 .enable_reg = 0x29d4,
461 .ns_reg = 0x29f4,
462 .md_reg = 0x29f0,
476 .src_sel_shift = 0,
481 .enable_reg = 0x29f4,
494 .halt_reg = 0x2fcc,
497 .enable_reg = 0x29f4,
512 .ns_reg = 0x2a34,
513 .md_reg = 0x2a30,
527 .src_sel_shift = 0,
532 .enable_reg = 0x2a34,
545 .halt_reg = 0x2fd0,
548 .enable_reg = 0x2a34,
563 .ns_reg = 0x2a54,
564 .md_reg = 0x2a50,
578 .src_sel_shift = 0,
583 .enable_reg = 0x2a54,
596 .halt_reg = 0x2fd0,
599 .enable_reg = 0x2a54,
614 .ns_reg = 0x2a74,
615 .md_reg = 0x2a70,
629 .src_sel_shift = 0,
634 .enable_reg = 0x2a74,
647 .halt_reg = 0x2fd0,
650 .enable_reg = 0x2a74,
665 .ns_reg = 0x2a94,
666 .md_reg = 0x2a90,
680 .src_sel_shift = 0,
685 .enable_reg = 0x2a94,
698 .halt_reg = 0x2fd0,
701 .enable_reg = 0x2a94,
721 { 25000000, P_PXO, 1, 0, 0 },
729 .ns_reg = 0x29cc,
730 .md_reg = 0x29c8,
744 .src_sel_shift = 0,
749 .enable_reg = 0x29cc,
762 .halt_reg = 0x2fcc,
765 .enable_reg = 0x29cc,
780 .ns_reg = 0x29ec,
781 .md_reg = 0x29e8,
795 .src_sel_shift = 0,
800 .enable_reg = 0x29ec,
813 .halt_reg = 0x2fcc,
816 .enable_reg = 0x29ec,
831 .ns_reg = 0x2a2c,
832 .md_reg = 0x2a28,
846 .src_sel_shift = 0,
851 .enable_reg = 0x2a2c,
864 .halt_reg = 0x2fd0,
867 .enable_reg = 0x2a2c,
882 .ns_reg = 0x2a4c,
883 .md_reg = 0x2a48,
897 .src_sel_shift = 0,
902 .enable_reg = 0x2a4c,
915 .halt_reg = 0x2fd0,
918 .enable_reg = 0x2a4c,
933 .ns_reg = 0x2a6c,
934 .md_reg = 0x2a68,
948 .src_sel_shift = 0,
953 .enable_reg = 0x2a6c,
966 .halt_reg = 0x2fd0,
969 .enable_reg = 0x2a6c,
984 .ns_reg = 0x2a8c,
985 .md_reg = 0x2a88,
999 .src_sel_shift = 0,
1004 .enable_reg = 0x2a8c,
1017 .halt_reg = 0x2fd0,
1020 .enable_reg = 0x2a8c,
1035 .hwcg_reg = 0x29c0,
1037 .halt_reg = 0x2fcc,
1040 .enable_reg = 0x29c0,
1050 .hwcg_reg = 0x29e0,
1052 .halt_reg = 0x2fcc,
1055 .enable_reg = 0x29e0,
1065 .hwcg_reg = 0x2a20,
1067 .halt_reg = 0x2fd0,
1070 .enable_reg = 0x2a20,
1081 .hwcg_reg = 0x2a40,
1083 .halt_reg = 0x2fd0,
1086 .enable_reg = 0x2a40,
1096 .hwcg_reg = 0x2a60,
1098 .halt_reg = 0x2fd0,
1101 .enable_reg = 0x2a60,
1111 .hwcg_reg = 0x2a80,
1113 .halt_reg = 0x2fd0,
1116 .enable_reg = 0x2a80,
1126 { 12500000, P_PXO, 2, 0, 0 },
1127 { 25000000, P_PXO, 1, 0, 0 },
1130 { 96000000, P_PLL8, 4, 0, 0 },
1131 { 128000000, P_PLL8, 3, 0, 0 },
1132 { 192000000, P_PLL8, 2, 0, 0 },
1137 .ns_reg = 0x2d24,
1138 .md_reg = 0x2d00,
1152 .src_sel_shift = 0,
1157 .enable_reg = 0x2d24,
1170 .halt_reg = 0x2fd8,
1173 .enable_reg = 0x2d24,
1188 .ns_reg = 0x2d44,
1189 .md_reg = 0x2d40,
1203 .src_sel_shift = 0,
1208 .enable_reg = 0x2d44,
1221 .halt_reg = 0x2fd8,
1224 .enable_reg = 0x2d44,
1239 .ns_reg = 0x2d64,
1240 .md_reg = 0x2d60,
1254 .src_sel_shift = 0,
1259 .enable_reg = 0x2d64,
1272 .halt_reg = 0x2fd8,
1275 .enable_reg = 0x2d64,
1290 .hwcg_reg = 0x25a0,
1292 .halt_reg = 0x2fc8,
1295 .enable_reg = 0x25a0,
1305 .ns_reg = 0x2e80,
1311 .src_sel_shift = 0,
1315 .enable_reg = 0x2e80,
1327 .halt_reg = 0x2fd8,
1331 .enable_reg = 0x3080,
1354 { 96000000, P_PLL8, 4, 0, 0 },
1355 { 192000000, P_PLL8, 2, 0, 0 },
1360 .ns_reg = 0x282c,
1361 .md_reg = 0x2828,
1375 .src_sel_shift = 0,
1380 .enable_reg = 0x282c,
1392 .halt_reg = 0x2fc8,
1395 .enable_reg = 0x282c,
1410 .ns_reg = 0x286c,
1411 .md_reg = 0x2868,
1425 .src_sel_shift = 0,
1430 .enable_reg = 0x286c,
1442 .halt_reg = 0x2fc8,
1445 .enable_reg = 0x286c,
1460 .hwcg_reg = 0x2820,
1462 .halt_reg = 0x2fc8,
1465 .enable_reg = 0x2820,
1475 .hwcg_reg = 0x2860,
1477 .halt_reg = 0x2fc8,
1480 .enable_reg = 0x2860,
1495 .ns_reg = 0x2710,
1496 .md_reg = 0x270c,
1510 .src_sel_shift = 0,
1515 .enable_reg = 0x2710,
1527 .halt_reg = 0x2fd4,
1530 .enable_reg = 0x2710,
1545 .hwcg_reg = 0x2700,
1547 .halt_reg = 0x2fd4,
1550 .enable_reg = 0x2700,
1560 .hwcg_reg = 0x25c0,
1562 .halt_reg = 0x2fc8,
1565 .enable_reg = 0x25c0,
1575 .halt_reg = 0x2fdc,
1579 .enable_reg = 0x3080,
1589 .hwcg_reg = 0x2208,
1591 .halt_reg = 0x2fdc,
1595 .enable_reg = 0x3080,
1605 .halt_reg = 0x2fd8,
1609 .enable_reg = 0x3080,
1619 .halt_reg = 0x2fd8,
1623 .enable_reg = 0x3080,
1633 .halt_reg = 0x2fd8,
1637 .enable_reg = 0x3080,
1647 .hwcg_reg = 0x27e0,
1649 .halt_reg = 0x2fd8,
1653 .enable_reg = 0x3080,
1663 { 100000000, P_PLL3, 12, 0, 0 },
1668 .ns_reg = 0x3860,
1674 .src_sel_shift = 0,
1679 .enable_reg = 0x3860,
1692 .halt_reg = 0x2fdc,
1695 .enable_reg = 0x3860,
1710 .halt_reg = 0x2fc0,
1713 .enable_reg = 0x22c0,
1723 .halt_reg = 0x2fdc,
1726 .enable_reg = 0x22c8,
1736 .halt_reg = 0x2fd4,
1739 .enable_reg = 0x22cc,
1749 .halt_reg = 0x2fdc,
1752 .enable_reg = 0x22d0,
1762 .ns_reg = 0x3aa0,
1768 .src_sel_shift = 0,
1773 .enable_reg = 0x3aa0,
1786 .halt_reg = 0x2fdc,
1789 .enable_reg = 0x3aa0,
1804 .halt_reg = 0x2fc0,
1807 .enable_reg = 0x3a80,
1817 .halt_reg = 0x2fdc,
1820 .enable_reg = 0x3a88,
1830 .halt_reg = 0x2fd4,
1833 .enable_reg = 0x3a8c,
1843 .halt_reg = 0x2fdc,
1846 .enable_reg = 0x3a90,
1856 .ns_reg = 0x3ae0,
1862 .src_sel_shift = 0,
1867 .enable_reg = 0x3ae0,
1880 .halt_reg = 0x2fdc,
1883 .enable_reg = 0x3ae0,
1898 .halt_reg = 0x2fc0,
1901 .enable_reg = 0x3ac0,
1911 .halt_reg = 0x2fdc,
1914 .enable_reg = 0x3ac8,
1924 .halt_reg = 0x2fd4,
1927 .enable_reg = 0x3acc,
1937 .halt_reg = 0x2fdc,
1940 .enable_reg = 0x3ad0,
1950 { 100000000, P_PLL3, 12, 0, 0 },
1955 .ns_reg = 0x2c08,
1961 .src_sel_shift = 0,
1966 .enable_reg = 0x2c08,
1979 .halt_reg = 0x2fdc,
1982 .enable_reg = 0x2c0c,
1997 .halt_reg = 0x2fdc,
2000 .enable_reg = 0x2c10,
2015 .halt_reg = 0x2fdc,
2018 .enable_reg = 0x2c14,
2030 .halt_reg = 0x2fc0,
2033 .enable_reg = 0x2c20,
2043 .halt_reg = 0x2fdc,
2046 .enable_reg = 0x2c00,
2056 .halt_reg = 0x2fc4,
2059 .enable_reg = 0x2480,
2069 .halt_reg = 0x2fcc,
2072 .enable_reg = 0x2c40,
2087 .ns_reg = 0x3b2c,
2088 .md_reg = 0x3b28,
2102 .src_sel_shift = 0,
2107 .enable_reg = 0x3b2c,
2120 .halt_reg = 0x2fc4,
2123 .enable_reg = 0x3b24,
2138 .halt_reg = 0x2fc4,
2141 .enable_reg = 0x3b34,
2161 .ns_reg = 0x3b44,
2162 .md_reg = 0x3b40,
2176 .src_sel_shift = 0,
2181 .enable_reg = 0x3b44,
2194 .halt_reg = 0x2fc4,
2197 .enable_reg = 0x3b48,
2212 .halt_reg = 0x2fc4,
2215 .enable_reg = 0x3b4c,
2235 .ns_reg = 0x290C,
2236 .md_reg = 0x2908,
2250 .src_sel_shift = 0,
2255 .enable_reg = 0x2968,
2268 .halt_reg = 0x2fcc,
2271 .enable_reg = 0x290c,
2286 .hwcg_reg = 0x2900,
2288 .halt_reg = 0x2fc8,
2291 .enable_reg = 0x2900,
2301 .ns_reg = 0x2968,
2302 .md_reg = 0x2964,
2316 .src_sel_shift = 0,
2321 .enable_reg = 0x2968,
2334 .halt_reg = 0x2fcc,
2337 .enable_reg = 0x2968,
2352 .halt_reg = 0x2fcc,
2355 .enable_reg = 0x296c,
2370 .halt_reg = 0x2fcc,
2373 .enable_reg = 0x2960,
2383 .hwcg_reg = 0x3b00,
2385 .halt_reg = 0x2fcc,
2388 .enable_reg = 0x3b00,
2398 .halt_reg = 0x2fcc,
2399 .halt_bit = 0,
2401 .enable_reg = 0x3b00,
2417 .ns_reg[0] = 0x3cac,
2418 .ns_reg[1] = 0x3cb0,
2419 .md_reg[0] = 0x3ca4,
2420 .md_reg[1] = 0x3ca8,
2421 .bank_reg = 0x3ca0,
2422 .mn[0] = {
2438 .s[0] = {
2439 .src_sel_shift = 0,
2443 .src_sel_shift = 0,
2446 .p[0] = {
2454 .mux_sel_bit = 0,
2457 .enable_reg = 0x3ca0,
2469 .halt_reg = 0x3c20,
2471 .hwcg_reg = 0x3cb4,
2474 .enable_reg = 0x3cb4,
2489 .ns_reg[0] = 0x3ccc,
2490 .ns_reg[1] = 0x3cd0,
2491 .md_reg[0] = 0x3cc4,
2492 .md_reg[1] = 0x3cc8,
2493 .bank_reg = 0x3ca0,
2494 .mn[0] = {
2510 .s[0] = {
2511 .src_sel_shift = 0,
2515 .src_sel_shift = 0,
2518 .p[0] = {
2526 .mux_sel_bit = 0,
2529 .enable_reg = 0x3cc0,
2541 .halt_reg = 0x3c20,
2543 .hwcg_reg = 0x3cd4,
2546 .enable_reg = 0x3cd4,
2561 .ns_reg[0] = 0x3cec,
2562 .ns_reg[1] = 0x3cf0,
2563 .md_reg[0] = 0x3ce4,
2564 .md_reg[1] = 0x3ce8,
2565 .bank_reg = 0x3ce0,
2566 .mn[0] = {
2582 .s[0] = {
2583 .src_sel_shift = 0,
2587 .src_sel_shift = 0,
2590 .p[0] = {
2598 .mux_sel_bit = 0,
2601 .enable_reg = 0x3ce0,
2613 .halt_reg = 0x3c20,
2615 .hwcg_reg = 0x3cf4,
2618 .enable_reg = 0x3cf4,
2633 .ns_reg[0] = 0x3d0c,
2634 .ns_reg[1] = 0x3d10,
2635 .md_reg[0] = 0x3d04,
2636 .md_reg[1] = 0x3d08,
2637 .bank_reg = 0x3d00,
2638 .mn[0] = {
2654 .s[0] = {
2655 .src_sel_shift = 0,
2659 .src_sel_shift = 0,
2662 .p[0] = {
2670 .mux_sel_bit = 0,
2673 .enable_reg = 0x3d00,
2685 .halt_reg = 0x3c20,
2687 .hwcg_reg = 0x3d14,
2690 .enable_reg = 0x3d14,
2705 { 266000000, P_PLL0, 3, 0, 0 },
2706 { 400000000, P_PLL0, 2, 0, 0 },
2711 .ns_reg[0] = 0x3dc4,
2712 .ns_reg[1] = 0x3dc8,
2713 .bank_reg = 0x3dc0,
2714 .s[0] = {
2715 .src_sel_shift = 0,
2719 .src_sel_shift = 0,
2722 .p[0] = {
2730 .mux_sel_bit = 0,
2733 .enable_reg = 0x3dc0,
2745 .halt_reg = 0x3c20,
2748 .enable_reg = 0x3dd0,
2764 { 275000000, P_PLL18, 2, 0, 0 },
2765 { 550000000, P_PLL18, 1, 0, 0 },
2766 { 733000000, P_PLL18, 1, 0, 0 },
2772 { 275000000, P_PLL18, 2, 0, 0 },
2773 { 600000000, P_PLL18, 1, 0, 0 },
2774 { 800000000, P_PLL18, 1, 0, 0 },
2779 .ns_reg[0] = 0x3d2c,
2780 .ns_reg[1] = 0x3d30,
2781 .md_reg[0] = 0x3d24,
2782 .md_reg[1] = 0x3d28,
2783 .bank_reg = 0x3d20,
2784 .mn[0] = {
2800 .s[0] = {
2801 .src_sel_shift = 0,
2805 .src_sel_shift = 0,
2808 .p[0] = {
2816 .mux_sel_bit = 0,
2819 .enable_reg = 0x3d20,
2832 .ns_reg[0] = 0x3d4c,
2833 .ns_reg[1] = 0x3d50,
2834 .md_reg[0] = 0x3d44,
2835 .md_reg[1] = 0x3d48,
2836 .bank_reg = 0x3d40,
2837 .mn[0] = {
2853 .s[0] = {
2854 .src_sel_shift = 0,
2858 .src_sel_shift = 0,
2861 .p[0] = {
2869 .mux_sel_bit = 0,
2872 .enable_reg = 0x3d40,
2891 .ns_reg[0] = 0x36C4,
2892 .ns_reg[1] = 0x36C8,
2893 .bank_reg = 0x36C0,
2894 .s[0] = {
2895 .src_sel_shift = 0,
2899 .src_sel_shift = 0,
2902 .p[0] = {
2910 .mux_sel_bit = 0,
2913 .enable_reg = 0x36C0,
2925 .halt_reg = 0x2FDC,
2927 .hwcg_reg = 0x36CC,
2930 .enable_reg = 0x36CC,
2951 .ns_reg[0] = 0x3d84,
2952 .ns_reg[1] = 0x3d88,
2953 .bank_reg = 0x3d80,
2954 .s[0] = {
2955 .src_sel_shift = 0,
2959 .src_sel_shift = 0,
2962 .p[0] = {
2970 .mux_sel_bit = 0,
2973 .enable_reg = 0x3d80,
2985 .halt_reg = 0x3c20,
2987 .hwcg_reg = 0x3d8c,
2990 .enable_reg = 0x3d8c,
3011 .ns_reg[0] = 0x3c64,
3012 .ns_reg[1] = 0x3c68,
3013 .bank_reg = 0x3c60,
3014 .s[0] = {
3015 .src_sel_shift = 0,
3019 .src_sel_shift = 0,
3022 .p[0] = {
3030 .mux_sel_bit = 0,
3033 .enable_reg = 0x3c60,
3045 .halt_reg = 0x3c20,
3047 .hwcg_reg = 0x3c6c,
3050 .enable_reg = 0x3c6c,
3195 [QDSS_STM_RESET] = { 0x2060, 6 },
3196 [AFAB_SMPSS_S_RESET] = { 0x20b8, 2 },
3197 [AFAB_SMPSS_M1_RESET] = { 0x20b8, 1 },
3198 [AFAB_SMPSS_M0_RESET] = { 0x20b8, 0 },
3199 [AFAB_EBI1_CH0_RESET] = { 0x20c0, 7 },
3200 [AFAB_EBI1_CH1_RESET] = { 0x20c4, 7 },
3201 [SFAB_ADM0_M0_RESET] = { 0x21e0, 7 },
3202 [SFAB_ADM0_M1_RESET] = { 0x21e4, 7 },
3203 [SFAB_ADM0_M2_RESET] = { 0x21e8, 7 },
3204 [ADM0_C2_RESET] = { 0x220c, 4 },
3205 [ADM0_C1_RESET] = { 0x220c, 3 },
3206 [ADM0_C0_RESET] = { 0x220c, 2 },
3207 [ADM0_PBUS_RESET] = { 0x220c, 1 },
3208 [ADM0_RESET] = { 0x220c, 0 },
3209 [QDSS_CLKS_SW_RESET] = { 0x2260, 5 },
3210 [QDSS_POR_RESET] = { 0x2260, 4 },
3211 [QDSS_TSCTR_RESET] = { 0x2260, 3 },
3212 [QDSS_HRESET_RESET] = { 0x2260, 2 },
3213 [QDSS_AXI_RESET] = { 0x2260, 1 },
3214 [QDSS_DBG_RESET] = { 0x2260, 0 },
3215 [SFAB_PCIE_M_RESET] = { 0x22d8, 1 },
3216 [SFAB_PCIE_S_RESET] = { 0x22d8, 0 },
3217 [PCIE_EXT_RESET] = { 0x22dc, 6 },
3218 [PCIE_PHY_RESET] = { 0x22dc, 5 },
3219 [PCIE_PCI_RESET] = { 0x22dc, 4 },
3220 [PCIE_POR_RESET] = { 0x22dc, 3 },
3221 [PCIE_HCLK_RESET] = { 0x22dc, 2 },
3222 [PCIE_ACLK_RESET] = { 0x22dc, 0 },
3223 [SFAB_LPASS_RESET] = { 0x23a0, 7 },
3224 [SFAB_AFAB_M_RESET] = { 0x23e0, 7 },
3225 [AFAB_SFAB_M0_RESET] = { 0x2420, 7 },
3226 [AFAB_SFAB_M1_RESET] = { 0x2424, 7 },
3227 [SFAB_SATA_S_RESET] = { 0x2480, 7 },
3228 [SFAB_DFAB_M_RESET] = { 0x2500, 7 },
3229 [DFAB_SFAB_M_RESET] = { 0x2520, 7 },
3230 [DFAB_SWAY0_RESET] = { 0x2540, 7 },
3231 [DFAB_SWAY1_RESET] = { 0x2544, 7 },
3232 [DFAB_ARB0_RESET] = { 0x2560, 7 },
3233 [DFAB_ARB1_RESET] = { 0x2564, 7 },
3234 [PPSS_PROC_RESET] = { 0x2594, 1 },
3235 [PPSS_RESET] = { 0x2594, 0 },
3236 [DMA_BAM_RESET] = { 0x25c0, 7 },
3237 [SPS_TIC_H_RESET] = { 0x2600, 7 },
3238 [SFAB_CFPB_M_RESET] = { 0x2680, 7 },
3239 [SFAB_CFPB_S_RESET] = { 0x26c0, 7 },
3240 [TSIF_H_RESET] = { 0x2700, 7 },
3241 [CE1_H_RESET] = { 0x2720, 7 },
3242 [CE1_CORE_RESET] = { 0x2724, 7 },
3243 [CE1_SLEEP_RESET] = { 0x2728, 7 },
3244 [CE2_H_RESET] = { 0x2740, 7 },
3245 [CE2_CORE_RESET] = { 0x2744, 7 },
3246 [SFAB_SFPB_M_RESET] = { 0x2780, 7 },
3247 [SFAB_SFPB_S_RESET] = { 0x27a0, 7 },
3248 [RPM_PROC_RESET] = { 0x27c0, 7 },
3249 [PMIC_SSBI2_RESET] = { 0x280c, 12 },
3250 [SDC1_RESET] = { 0x2830, 0 },
3251 [SDC2_RESET] = { 0x2850, 0 },
3252 [SDC3_RESET] = { 0x2870, 0 },
3253 [SDC4_RESET] = { 0x2890, 0 },
3254 [USB_HS1_RESET] = { 0x2910, 0 },
3255 [USB_HSIC_RESET] = { 0x2934, 0 },
3256 [USB_FS1_XCVR_RESET] = { 0x2974, 1 },
3257 [USB_FS1_RESET] = { 0x2974, 0 },
3258 [GSBI1_RESET] = { 0x29dc, 0 },
3259 [GSBI2_RESET] = { 0x29fc, 0 },
3260 [GSBI3_RESET] = { 0x2a1c, 0 },
3261 [GSBI4_RESET] = { 0x2a3c, 0 },
3262 [GSBI5_RESET] = { 0x2a5c, 0 },
3263 [GSBI6_RESET] = { 0x2a7c, 0 },
3264 [GSBI7_RESET] = { 0x2a9c, 0 },
3265 [SPDM_RESET] = { 0x2b6c, 0 },
3266 [SEC_CTRL_RESET] = { 0x2b80, 7 },
3267 [TLMM_H_RESET] = { 0x2ba0, 7 },
3268 [SFAB_SATA_M_RESET] = { 0x2c18, 0 },
3269 [SATA_RESET] = { 0x2c1c, 0 },
3270 [TSSC_RESET] = { 0x2ca0, 7 },
3271 [PDM_RESET] = { 0x2cc0, 12 },
3272 [MPM_H_RESET] = { 0x2da0, 7 },
3273 [MPM_RESET] = { 0x2da4, 0 },
3274 [SFAB_SMPSS_S_RESET] = { 0x2e00, 7 },
3275 [PRNG_RESET] = { 0x2e80, 12 },
3276 [SFAB_CE3_M_RESET] = { 0x36c8, 1 },
3277 [SFAB_CE3_S_RESET] = { 0x36c8, 0 },
3278 [CE3_SLEEP_RESET] = { 0x36d0, 7 },
3279 [PCIE_1_M_RESET] = { 0x3a98, 1 },
3280 [PCIE_1_S_RESET] = { 0x3a98, 0 },
3281 [PCIE_1_EXT_RESET] = { 0x3a9c, 6 },
3282 [PCIE_1_PHY_RESET] = { 0x3a9c, 5 },
3283 [PCIE_1_PCI_RESET] = { 0x3a9c, 4 },
3284 [PCIE_1_POR_RESET] = { 0x3a9c, 3 },
3285 [PCIE_1_HCLK_RESET] = { 0x3a9c, 2 },
3286 [PCIE_1_ACLK_RESET] = { 0x3a9c, 0 },
3287 [PCIE_2_M_RESET] = { 0x3ad8, 1 },
3288 [PCIE_2_S_RESET] = { 0x3ad8, 0 },
3289 [PCIE_2_EXT_RESET] = { 0x3adc, 6 },
3290 [PCIE_2_PHY_RESET] = { 0x3adc, 5 },
3291 [PCIE_2_PCI_RESET] = { 0x3adc, 4 },
3292 [PCIE_2_POR_RESET] = { 0x3adc, 3 },
3293 [PCIE_2_HCLK_RESET] = { 0x3adc, 2 },
3294 [PCIE_2_ACLK_RESET] = { 0x3adc, 0 },
3295 [SFAB_USB30_S_RESET] = { 0x3b54, 1 },
3296 [SFAB_USB30_M_RESET] = { 0x3b54, 0 },
3297 [USB30_0_PORT2_HS_PHY_RESET] = { 0x3b50, 5 },
3298 [USB30_0_MASTER_RESET] = { 0x3b50, 4 },
3299 [USB30_0_SLEEP_RESET] = { 0x3b50, 3 },
3300 [USB30_0_UTMI_PHY_RESET] = { 0x3b50, 2 },
3301 [USB30_0_POWERON_RESET] = { 0x3b50, 1 },
3302 [USB30_0_PHY_RESET] = { 0x3b50, 0 },
3303 [USB30_1_MASTER_RESET] = { 0x3b58, 4 },
3304 [USB30_1_SLEEP_RESET] = { 0x3b58, 3 },
3305 [USB30_1_UTMI_PHY_RESET] = { 0x3b58, 2 },
3306 [USB30_1_POWERON_RESET] = { 0x3b58, 1 },
3307 [USB30_1_PHY_RESET] = { 0x3b58, 0 },
3308 [NSSFB0_RESET] = { 0x3b60, 6 },
3309 [NSSFB1_RESET] = { 0x3b60, 7 },
3310 [UBI32_CORE1_CLKRST_CLAMP_RESET] = { 0x3d3c, 3},
3311 [UBI32_CORE1_CLAMP_RESET] = { 0x3d3c, 2 },
3312 [UBI32_CORE1_AHB_RESET] = { 0x3d3c, 1 },
3313 [UBI32_CORE1_AXI_RESET] = { 0x3d3c, 0 },
3314 [UBI32_CORE2_CLKRST_CLAMP_RESET] = { 0x3d5c, 3 },
3315 [UBI32_CORE2_CLAMP_RESET] = { 0x3d5c, 2 },
3316 [UBI32_CORE2_AHB_RESET] = { 0x3d5c, 1 },
3317 [UBI32_CORE2_AXI_RESET] = { 0x3d5c, 0 },
3318 [GMAC_CORE1_RESET] = { 0x3cbc, 0 },
3319 [GMAC_CORE2_RESET] = { 0x3cdc, 0 },
3320 [GMAC_CORE3_RESET] = { 0x3cfc, 0 },
3321 [GMAC_CORE4_RESET] = { 0x3d1c, 0 },
3322 [GMAC_AHB_RESET] = { 0x3e24, 0 },
3323 [CRYPTO_ENG1_RESET] = { 0x3e00, 0},
3324 [CRYPTO_ENG2_RESET] = { 0x3e04, 0},
3325 [CRYPTO_ENG3_RESET] = { 0x3e08, 0},
3326 [CRYPTO_ENG4_RESET] = { 0x3e0c, 0},
3327 [CRYPTO_AHB_RESET] = { 0x3e10, 0},
3328 [NSS_CH0_RST_RX_CLK_N_RESET] = { 0x3b60, 0 },
3329 [NSS_CH0_RST_TX_CLK_N_RESET] = { 0x3b60, 1 },
3330 [NSS_CH0_RST_RX_125M_N_RESET] = { 0x3b60, 2 },
3331 [NSS_CH0_HW_RST_RX_125M_N_RESET] = { 0x3b60, 3 },
3332 [NSS_CH0_RST_TX_125M_N_RESET] = { 0x3b60, 4 },
3333 [NSS_CH1_RST_RX_CLK_N_RESET] = { 0x3b60, 5 },
3334 [NSS_CH1_RST_TX_CLK_N_RESET] = { 0x3b60, 6 },
3335 [NSS_CH1_RST_RX_125M_N_RESET] = { 0x3b60, 7 },
3336 [NSS_CH1_HW_RST_RX_125M_N_RESET] = { 0x3b60, 8 },
3337 [NSS_CH1_RST_TX_125M_N_RESET] = { 0x3b60, 9 },
3338 [NSS_CH2_RST_RX_CLK_N_RESET] = { 0x3b60, 10 },
3339 [NSS_CH2_RST_TX_CLK_N_RESET] = { 0x3b60, 11 },
3340 [NSS_CH2_RST_RX_125M_N_RESET] = { 0x3b60, 12 },
3341 [NSS_CH2_HW_RST_RX_125M_N_RESET] = { 0x3b60, 13 },
3342 [NSS_CH2_RST_TX_125M_N_RESET] = { 0x3b60, 14 },
3343 [NSS_CH3_RST_RX_CLK_N_RESET] = { 0x3b60, 15 },
3344 [NSS_CH3_RST_TX_CLK_N_RESET] = { 0x3b60, 16 },
3345 [NSS_CH3_RST_RX_125M_N_RESET] = { 0x3b60, 17 },
3346 [NSS_CH3_HW_RST_RX_125M_N_RESET] = { 0x3b60, 18 },
3347 [NSS_CH3_RST_TX_125M_N_RESET] = { 0x3b60, 19 },
3348 [NSS_RST_RX_250M_125M_N_RESET] = { 0x3b60, 20 },
3349 [NSS_RST_TX_250M_125M_N_RESET] = { 0x3b60, 21 },
3350 [NSS_QSGMII_TXPI_RST_N_RESET] = { 0x3b60, 22 },
3351 [NSS_QSGMII_CDR_RST_N_RESET] = { 0x3b60, 23 },
3352 [NSS_SGMII2_CDR_RST_N_RESET] = { 0x3b60, 24 },
3353 [NSS_SGMII3_CDR_RST_N_RESET] = { 0x3b60, 25 },
3354 [NSS_CAL_PRBS_RST_N_RESET] = { 0x3b60, 26 },
3355 [NSS_LCKDT_RST_N_RESET] = { 0x3b60, 27 },
3356 [NSS_SRDS_N_RESET] = { 0x3b60, 28 },
3363 .max_register = 0x3e40,
3412 regmap_update_bits(regmap, 0x31a4, 0xffffffc0, 0x40000400); in gcc_ipq806x_probe()
3413 regmap_write(regmap, 0x31b0, 0x3080); in gcc_ipq806x_probe()
3416 regmap_write(regmap, 0x3cb8, 8); in gcc_ipq806x_probe()
3417 regmap_write(regmap, 0x3cd8, 8); in gcc_ipq806x_probe()
3418 regmap_write(regmap, 0x3cf8, 8); in gcc_ipq806x_probe()
3419 regmap_write(regmap, 0x3d18, 8); in gcc_ipq806x_probe()