Lines Matching +full:0 +full:x8014
52 #define DISP_CC_MISC_CMD 0xF000
75 { 249600000, 2000000000, 0 },
79 .l = 0xD,
80 .alpha = 0x6492,
81 .config_ctl_val = 0x20485699,
82 .config_ctl_hi_val = 0x00182261,
83 .config_ctl_hi1_val = 0x32AA299C,
84 .user_ctl_val = 0x00000000,
85 .user_ctl_hi_val = 0x00000805,
89 .offset = 0x0,
106 .l = 0x1F,
107 .alpha = 0x4000,
108 .config_ctl_val = 0x20485699,
109 .config_ctl_hi_val = 0x00182261,
110 .config_ctl_hi1_val = 0x32AA299C,
111 .user_ctl_val = 0x00000000,
112 .user_ctl_hi_val = 0x00000805,
116 .offset = 0x1000,
133 { P_BI_TCXO, 0 },
151 { P_BI_TCXO, 0 },
163 { P_BI_TCXO, 0 },
179 { P_BI_TCXO, 0 },
195 { P_BI_TCXO, 0 },
207 { P_BI_TCXO, 0 },
221 { P_BI_TCXO, 0 },
233 { P_SLEEP_CLK, 0 },
241 F(19200000, P_BI_TCXO, 1, 0, 0),
242 F(37500000, P_DISP_CC_PLL1_OUT_MAIN, 16, 0, 0),
243 F(75000000, P_DISP_CC_PLL1_OUT_MAIN, 8, 0, 0),
248 .cmd_rcgr = 0x8324,
249 .mnd_width = 0,
263 F(19200000, P_BI_TCXO, 1, 0, 0),
268 .cmd_rcgr = 0x8134,
269 .mnd_width = 0,
283 .cmd_rcgr = 0x8150,
284 .mnd_width = 0,
298 .cmd_rcgr = 0x81ec,
299 .mnd_width = 0,
313 F(162000, P_DP0_PHY_PLL_LINK_CLK, 1, 0, 0),
314 F(270000, P_DP0_PHY_PLL_LINK_CLK, 1, 0, 0),
315 F(540000, P_DP0_PHY_PLL_LINK_CLK, 1, 0, 0),
316 F(810000, P_DP0_PHY_PLL_LINK_CLK, 1, 0, 0),
321 .cmd_rcgr = 0x819c,
322 .mnd_width = 0,
336 .cmd_rcgr = 0x81bc,
351 .cmd_rcgr = 0x81d4,
366 .cmd_rcgr = 0x8254,
367 .mnd_width = 0,
381 .cmd_rcgr = 0x8234,
382 .mnd_width = 0,
396 .cmd_rcgr = 0x8204,
411 .cmd_rcgr = 0x821c,
426 .cmd_rcgr = 0x82bc,
427 .mnd_width = 0,
441 .cmd_rcgr = 0x826c,
442 .mnd_width = 0,
456 .cmd_rcgr = 0x828c,
471 .cmd_rcgr = 0x82a4,
486 .cmd_rcgr = 0x8308,
487 .mnd_width = 0,
501 .cmd_rcgr = 0x82ec,
502 .mnd_width = 0,
516 .cmd_rcgr = 0x82d4,
531 .cmd_rcgr = 0x816c,
532 .mnd_width = 0,
546 .cmd_rcgr = 0x8184,
547 .mnd_width = 0,
561 F(19200000, P_BI_TCXO, 1, 0, 0),
562 F(85714286, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
563 F(100000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
564 F(150000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
565 F(172000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
566 F(200000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
567 F(325000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
568 F(375000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
569 F(500000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
574 .cmd_rcgr = 0x80ec,
575 .mnd_width = 0,
589 .cmd_rcgr = 0x80bc,
604 .cmd_rcgr = 0x80d4,
619 F(19200000, P_BI_TCXO, 1, 0, 0),
620 F(150000000, P_DISP_CC_PLL1_OUT_MAIN, 4, 0, 0),
621 F(200000000, P_DISP_CC_PLL1_OUT_MAIN, 3, 0, 0),
622 F(300000000, P_DISP_CC_PLL1_OUT_MAIN, 2, 0, 0),
627 .cmd_rcgr = 0x8104,
628 .mnd_width = 0,
642 .cmd_rcgr = 0x811c,
643 .mnd_width = 0,
657 F(32000, P_SLEEP_CLK, 1, 0, 0),
662 .cmd_rcgr = 0xe060,
663 .mnd_width = 0,
677 .cmd_rcgr = 0xe044,
678 .mnd_width = 0,
692 .reg = 0x814c,
693 .shift = 0,
706 .reg = 0x8168,
707 .shift = 0,
720 .reg = 0x81b4,
721 .shift = 0,
735 .reg = 0x824c,
736 .shift = 0,
750 .reg = 0x8284,
751 .shift = 0,
765 .reg = 0x8304,
766 .shift = 0,
780 .halt_reg = 0xa020,
783 .enable_reg = 0xa020,
784 .enable_mask = BIT(0),
798 .halt_reg = 0x80a4,
801 .enable_reg = 0x80a4,
802 .enable_mask = BIT(0),
816 .halt_reg = 0x8028,
819 .enable_reg = 0x8028,
820 .enable_mask = BIT(0),
834 .halt_reg = 0x802c,
837 .enable_reg = 0x802c,
838 .enable_mask = BIT(0),
852 .halt_reg = 0x8030,
855 .enable_reg = 0x8030,
856 .enable_mask = BIT(0),
870 .halt_reg = 0x8034,
873 .enable_reg = 0x8034,
874 .enable_mask = BIT(0),
888 .halt_reg = 0x8058,
891 .enable_reg = 0x8058,
892 .enable_mask = BIT(0),
906 .halt_reg = 0x804c,
909 .enable_reg = 0x804c,
910 .enable_mask = BIT(0),
924 .halt_reg = 0x8040,
927 .enable_reg = 0x8040,
928 .enable_mask = BIT(0),
942 .halt_reg = 0x8048,
945 .enable_reg = 0x8048,
946 .enable_mask = BIT(0),
960 .halt_reg = 0x8050,
963 .enable_reg = 0x8050,
964 .enable_mask = BIT(0),
978 .halt_reg = 0x8054,
981 .enable_reg = 0x8054,
982 .enable_mask = BIT(0),
996 .halt_reg = 0x8044,
999 .enable_reg = 0x8044,
1000 .enable_mask = BIT(0),
1014 .halt_reg = 0x8074,
1017 .enable_reg = 0x8074,
1018 .enable_mask = BIT(0),
1032 .halt_reg = 0x8070,
1035 .enable_reg = 0x8070,
1036 .enable_mask = BIT(0),
1050 .halt_reg = 0x8064,
1053 .enable_reg = 0x8064,
1054 .enable_mask = BIT(0),
1068 .halt_reg = 0x806c,
1071 .enable_reg = 0x806c,
1072 .enable_mask = BIT(0),
1086 .halt_reg = 0x805c,
1089 .enable_reg = 0x805c,
1090 .enable_mask = BIT(0),
1104 .halt_reg = 0x8060,
1107 .enable_reg = 0x8060,
1108 .enable_mask = BIT(0),
1122 .halt_reg = 0x8068,
1125 .enable_reg = 0x8068,
1126 .enable_mask = BIT(0),
1140 .halt_reg = 0x808c,
1143 .enable_reg = 0x808c,
1144 .enable_mask = BIT(0),
1158 .halt_reg = 0x8088,
1161 .enable_reg = 0x8088,
1162 .enable_mask = BIT(0),
1176 .halt_reg = 0x8080,
1179 .enable_reg = 0x8080,
1180 .enable_mask = BIT(0),
1194 .halt_reg = 0x8084,
1197 .enable_reg = 0x8084,
1198 .enable_mask = BIT(0),
1212 .halt_reg = 0x8078,
1215 .enable_reg = 0x8078,
1216 .enable_mask = BIT(0),
1230 .halt_reg = 0x807c,
1233 .enable_reg = 0x807c,
1234 .enable_mask = BIT(0),
1248 .halt_reg = 0x809c,
1251 .enable_reg = 0x809c,
1252 .enable_mask = BIT(0),
1266 .halt_reg = 0x80a0,
1269 .enable_reg = 0x80a0,
1270 .enable_mask = BIT(0),
1284 .halt_reg = 0x8094,
1287 .enable_reg = 0x8094,
1288 .enable_mask = BIT(0),
1302 .halt_reg = 0x8098,
1305 .enable_reg = 0x8098,
1306 .enable_mask = BIT(0),
1320 .halt_reg = 0x8090,
1323 .enable_reg = 0x8090,
1324 .enable_mask = BIT(0),
1338 .halt_reg = 0x8038,
1341 .enable_reg = 0x8038,
1342 .enable_mask = BIT(0),
1356 .halt_reg = 0x803c,
1359 .enable_reg = 0x803c,
1360 .enable_mask = BIT(0),
1374 .halt_reg = 0xa004,
1377 .enable_reg = 0xa004,
1378 .enable_mask = BIT(0),
1392 .halt_reg = 0x800c,
1395 .enable_reg = 0x800c,
1396 .enable_mask = BIT(0),
1410 .halt_reg = 0xa014,
1413 .enable_reg = 0xa014,
1414 .enable_mask = BIT(0),
1428 .halt_reg = 0x801c,
1431 .enable_reg = 0x801c,
1432 .enable_mask = BIT(0),
1446 .halt_reg = 0xc004,
1449 .enable_reg = 0xc004,
1450 .enable_mask = BIT(0),
1464 .halt_reg = 0x8004,
1467 .enable_reg = 0x8004,
1468 .enable_mask = BIT(0),
1482 .halt_reg = 0x8008,
1485 .enable_reg = 0x8008,
1486 .enable_mask = BIT(0),
1500 .halt_reg = 0xa00c,
1503 .enable_reg = 0xa00c,
1504 .enable_mask = BIT(0),
1518 .halt_reg = 0x8014,
1521 .enable_reg = 0x8014,
1522 .enable_mask = BIT(0),
1536 .halt_reg = 0xc00c,
1539 .enable_reg = 0xc00c,
1540 .enable_mask = BIT(0),
1554 .halt_reg = 0xc008,
1557 .enable_reg = 0xc008,
1558 .enable_mask = BIT(0),
1572 .halt_reg = 0xa01c,
1575 .enable_reg = 0xa01c,
1576 .enable_mask = BIT(0),
1590 .halt_reg = 0x8024,
1593 .enable_reg = 0x8024,
1594 .enable_mask = BIT(0),
1608 .halt_reg = 0xe078,
1611 .enable_reg = 0xe078,
1612 .enable_mask = BIT(0),
1626 .gdscr = 0x9000,
1635 .gdscr = 0xb000,
1731 [DISP_CC_MDSS_CORE_BCR] = { 0x8000 },
1732 [DISP_CC_MDSS_CORE_INT2_BCR] = { 0xa000 },
1733 [DISP_CC_MDSS_RSCC_BCR] = { 0xc000 },
1745 .max_register = 0x11008,
1793 regmap_update_bits(regmap, DISP_CC_MISC_CMD, 0x10, 0x10); in disp_cc_sm8450_probe()
1799 regmap_update_bits(regmap, 0xe05c, BIT(0), BIT(0)); in disp_cc_sm8450_probe()