Lines Matching +full:0 +full:x1040
35 { 249600000, 2000000000, 0 },
39 .l = 0x3a,
40 .alpha = 0x5555,
41 .config_ctl_val = 0x20485699,
42 .config_ctl_hi_val = 0x00002067,
43 .test_ctl_val = 0x40000000,
44 .test_ctl_hi_val = 0x00000002,
45 .user_ctl_val = 0x00000000,
46 .user_ctl_hi_val = 0x00004805,
50 .offset = 0x0,
67 { P_BI_TCXO, 0 },
79 { P_BI_TCXO, 0 },
89 { P_BI_TCXO, 0 },
103 { P_BI_TCXO, 0 },
113 { P_BI_TCXO, 0 },
123 { P_BI_TCXO, 0 },
131 F(19200000, P_BI_TCXO, 1, 0, 0),
132 F(37500000, P_GCC_DISP_GPLL0_CLK, 16, 0, 0),
133 F(75000000, P_GCC_DISP_GPLL0_CLK, 8, 0, 0),
138 .cmd_rcgr = 0x115c,
139 .mnd_width = 0,
153 .cmd_rcgr = 0x10c4,
154 .mnd_width = 0,
167 .reg = 0x10dc,
168 .shift = 0,
182 F(19200000, P_BI_TCXO, 1, 0, 0),
187 .cmd_rcgr = 0x1144,
188 .mnd_width = 0,
202 F(108000, P_DP_PHY_PLL_LINK_CLK, 3, 0, 0),
203 F(180000, P_DP_PHY_PLL_LINK_CLK, 3, 0, 0),
204 F(360000, P_DP_PHY_PLL_LINK_CLK, 1.5, 0, 0),
205 F(540000, P_DP_PHY_PLL_LINK_CLK, 1.5, 0, 0),
210 .cmd_rcgr = 0x1114,
211 .mnd_width = 0,
225 F(162000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0),
226 F(270000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0),
227 F(540000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0),
228 F(810000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0),
233 .cmd_rcgr = 0x10f8,
234 .mnd_width = 0,
248 .cmd_rcgr = 0x112c,
262 .cmd_rcgr = 0x10e0,
263 .mnd_width = 0,
276 F(19200000, P_BI_TCXO, 1, 0, 0),
277 F(200000000, P_GCC_DISP_GPLL0_CLK, 3, 0, 0),
278 F(300000000, P_GCC_DISP_GPLL0_CLK, 2, 0, 0),
279 F(373333333, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
280 F(448000000, P_DISP_CC_PLL0_OUT_MAIN, 2.5, 0, 0),
281 F(560000000, P_DISP_CC_PLL0_OUT_MAIN, 2, 0, 0),
286 .cmd_rcgr = 0x107c,
287 .mnd_width = 0,
301 .cmd_rcgr = 0x1064,
315 .cmd_rcgr = 0x1094,
316 .mnd_width = 0,
330 .cmd_rcgr = 0x10ac,
331 .mnd_width = 0,
344 .reg = 0x1110,
345 .shift = 0,
359 .halt_reg = 0x104c,
362 .enable_reg = 0x104c,
363 .enable_mask = BIT(0),
377 .halt_reg = 0x102c,
380 .enable_reg = 0x102c,
381 .enable_mask = BIT(0),
395 .halt_reg = 0x1030,
398 .enable_reg = 0x1030,
399 .enable_mask = BIT(0),
413 .halt_reg = 0x1048,
416 .enable_reg = 0x1048,
417 .enable_mask = BIT(0),
431 .halt_reg = 0x1040,
434 .enable_reg = 0x1040,
435 .enable_mask = BIT(0),
449 .halt_reg = 0x1038,
452 .enable_reg = 0x1038,
453 .enable_mask = BIT(0),
467 .halt_reg = 0x103c,
470 .enable_reg = 0x103c,
471 .enable_mask = BIT(0),
485 .halt_reg = 0x1044,
488 .enable_reg = 0x1044,
489 .enable_mask = BIT(0),
503 .halt_reg = 0x1034,
506 .enable_reg = 0x1034,
507 .enable_mask = BIT(0),
521 .halt_reg = 0x1010,
524 .enable_reg = 0x1010,
525 .enable_mask = BIT(0),
539 .halt_reg = 0x1020,
542 .enable_reg = 0x1020,
543 .enable_mask = BIT(0),
557 .halt_reg = 0x2004,
560 .enable_reg = 0x2004,
561 .enable_mask = BIT(0),
575 .halt_reg = 0x100c,
578 .enable_reg = 0x100c,
579 .enable_mask = BIT(0),
593 .halt_reg = 0x1018,
596 .enable_reg = 0x1018,
597 .enable_mask = BIT(0),
611 .halt_reg = 0x200c,
614 .enable_reg = 0x200c,
615 .enable_mask = BIT(0),
629 .halt_reg = 0x2008,
632 .enable_reg = 0x2008,
633 .enable_mask = BIT(0),
647 .halt_reg = 0x1028,
650 .enable_reg = 0x1028,
651 .enable_mask = BIT(0),
665 .halt_reg = 0x5004,
668 .enable_reg = 0x5004,
669 .enable_mask = BIT(0),
678 .halt_reg = 0x5008,
681 .enable_reg = 0x5008,
682 .enable_mask = BIT(0),
692 .gdscr = 0x1004,
745 .max_register = 0x10000,