Lines Matching +full:0 +full:x104c
34 { 249600000, 2000000000, 0 },
39 .l = 0x4F,
40 .alpha = 0x2AAA,
41 .config_ctl_val = 0x20485699,
42 .config_ctl_hi_val = 0x00002261,
43 .config_ctl_hi1_val = 0x329A299C,
44 .user_ctl_val = 0x00000001,
45 .user_ctl_hi_val = 0x00000805,
46 .user_ctl_hi1_val = 0x00000000,
50 .offset = 0x0,
67 { P_BI_TCXO, 0 },
75 { P_BI_TCXO, 0 },
87 { P_BI_TCXO, 0 },
97 { P_BI_TCXO, 0 },
109 { P_BI_TCXO, 0 },
123 { P_BI_TCXO, 0 },
133 { P_BI_TCXO, 0 },
143 F(19200000, P_BI_TCXO, 1, 0, 0),
144 F(37500000, P_GCC_DISP_GPLL0_CLK, 16, 0, 0),
145 F(75000000, P_GCC_DISP_GPLL0_CLK, 8, 0, 0),
150 .cmd_rcgr = 0x1170,
151 .mnd_width = 0,
164 .cmd_rcgr = 0x10d8,
165 .mnd_width = 0,
178 F(19200000, P_BI_TCXO, 1, 0, 0),
183 .cmd_rcgr = 0x1158,
184 .mnd_width = 0,
197 .cmd_rcgr = 0x1128,
198 .mnd_width = 0,
210 .cmd_rcgr = 0x110c,
211 .mnd_width = 0,
223 .cmd_rcgr = 0x1140,
236 .cmd_rcgr = 0x11d0,
237 .mnd_width = 0,
250 .cmd_rcgr = 0x11a0,
251 .mnd_width = 0,
264 .cmd_rcgr = 0x1188,
277 .cmd_rcgr = 0x10f4,
278 .mnd_width = 0,
291 F(200000000, P_GCC_DISP_GPLL0_CLK, 3, 0, 0),
292 F(300000000, P_GCC_DISP_GPLL0_CLK, 2, 0, 0),
293 F(380000000, P_DISP_CC_PLL0_OUT_MAIN, 4, 0, 0),
294 F(506666667, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
295 F(608000000, P_DISP_CC_PLL0_OUT_MAIN, 2.5, 0, 0),
300 .cmd_rcgr = 0x1090,
301 .mnd_width = 0,
314 .cmd_rcgr = 0x1078,
328 .cmd_rcgr = 0x10a8,
329 .mnd_width = 0,
342 .cmd_rcgr = 0x10c0,
343 .mnd_width = 0,
356 .reg = 0x10f0,
357 .shift = 0,
370 .reg = 0x1124,
371 .shift = 0,
384 .reg = 0x11b8,
385 .shift = 0,
398 .halt_reg = 0x1050,
401 .enable_reg = 0x1050,
402 .enable_mask = BIT(0),
416 .halt_reg = 0x1030,
419 .enable_reg = 0x1030,
420 .enable_mask = BIT(0),
434 .halt_reg = 0x1034,
437 .enable_reg = 0x1034,
438 .enable_mask = BIT(0),
452 .halt_reg = 0x104c,
455 .enable_reg = 0x104c,
456 .enable_mask = BIT(0),
470 .halt_reg = 0x1044,
473 .enable_reg = 0x1044,
474 .enable_mask = BIT(0),
488 .halt_reg = 0x103c,
491 .enable_reg = 0x103c,
492 .enable_mask = BIT(0),
506 .halt_reg = 0x1040,
509 .enable_reg = 0x1040,
510 .enable_mask = BIT(0),
524 .halt_reg = 0x1048,
527 .enable_reg = 0x1048,
528 .enable_mask = BIT(0),
542 .halt_reg = 0x1060,
545 .enable_reg = 0x1060,
546 .enable_mask = BIT(0),
560 .halt_reg = 0x1058,
563 .enable_reg = 0x1058,
564 .enable_mask = BIT(0),
578 .halt_reg = 0x105c,
581 .enable_reg = 0x105c,
582 .enable_mask = BIT(0),
596 .halt_reg = 0x1054,
599 .enable_reg = 0x1054,
600 .enable_mask = BIT(0),
614 .halt_reg = 0x1038,
617 .enable_reg = 0x1038,
618 .enable_mask = BIT(0),
632 .halt_reg = 0x1014,
635 .enable_reg = 0x1014,
636 .enable_mask = BIT(0),
650 .halt_reg = 0x1024,
653 .enable_reg = 0x1024,
654 .enable_mask = BIT(0),
668 .halt_reg = 0x2004,
671 .enable_reg = 0x2004,
672 .enable_mask = BIT(0),
686 .halt_reg = 0x1010,
689 .enable_reg = 0x1010,
690 .enable_mask = BIT(0),
704 .halt_reg = 0x101c,
707 .enable_reg = 0x101c,
708 .enable_mask = BIT(0),
722 .halt_reg = 0x200c,
725 .enable_reg = 0x200c,
726 .enable_mask = BIT(0),
740 .halt_reg = 0x2008,
743 .enable_reg = 0x2008,
744 .enable_mask = BIT(0),
758 .halt_reg = 0x102c,
761 .enable_reg = 0x102c,
762 .enable_mask = BIT(0),
776 .halt_reg = 0x5004,
779 .enable_reg = 0x5004,
780 .enable_mask = BIT(0),
789 .gdscr = 0x1004,
790 .en_rest_wait_val = 0x2,
791 .en_few_wait_val = 0x2,
792 .clk_dis_wait_val = 0xf,
853 .max_register = 0x10000,
885 regmap_update_bits(regmap, 0x5008, BIT(0), BIT(0)); in disp_cc_sc7280_probe()