13 #include <linux/regmap.h>
31 	ret = regmap_read(pll->clkr.regmap, pll->mode_reg, &val);  in clk_pll_enable()
40 	ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_BYPASSNL,  in clk_pll_enable()
52 	ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_RESET_N,  in clk_pll_enable()
61 	return regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_OUTCTRL,  in clk_pll_enable()
71 	regmap_read(pll->clkr.regmap, pll->mode_reg, &val);  in clk_pll_disable()
76 	regmap_update_bits(pll->clkr.regmap, pll->mode_reg, mask, 0);  in clk_pll_disable()
87 	regmap_read(pll->clkr.regmap, pll->l_reg, &l);  in clk_pll_recalc_rate()
88 	regmap_read(pll->clkr.regmap, pll->m_reg, &m);  in clk_pll_recalc_rate()
89 	regmap_read(pll->clkr.regmap, pll->n_reg, &n);  in clk_pll_recalc_rate()
103 		regmap_read(pll->clkr.regmap, pll->config_reg, &config);  in clk_pll_recalc_rate()
153 	regmap_read(pll->clkr.regmap, pll->mode_reg, &mode);  in clk_pll_set_rate()
159 	regmap_update_bits(pll->clkr.regmap, pll->l_reg, 0x3ff, f->l);  in clk_pll_set_rate()
160 	regmap_update_bits(pll->clkr.regmap, pll->m_reg, 0x7ffff, f->m);  in clk_pll_set_rate()
161 	regmap_update_bits(pll->clkr.regmap, pll->n_reg, 0x7ffff, f->n);  in clk_pll_set_rate()
162 	regmap_write(pll->clkr.regmap, pll->config_reg, f->ibits);  in clk_pll_set_rate()
188 		ret = regmap_read(pll->clkr.regmap, pll->status_reg, &val);  in wait_for_pll()
218 static void clk_pll_configure(struct clk_pll *pll, struct regmap *regmap,  in clk_pll_configure()  argument
224 	regmap_write(regmap, pll->l_reg, config->l);  in clk_pll_configure()
225 	regmap_write(regmap, pll->m_reg, config->m);  in clk_pll_configure()
226 	regmap_write(regmap, pll->n_reg, config->n);  in clk_pll_configure()
242 	regmap_update_bits(regmap, pll->config_reg, mask, val);  in clk_pll_configure()
245 void clk_pll_configure_sr(struct clk_pll *pll, struct regmap *regmap,  in clk_pll_configure_sr()  argument
248 	clk_pll_configure(pll, regmap, config);  in clk_pll_configure_sr()
250 		qcom_pll_set_fsm_mode(regmap, pll->mode_reg, 1, 8);  in clk_pll_configure_sr()
254 void clk_pll_configure_sr_hpm_lp(struct clk_pll *pll, struct regmap *regmap,  in clk_pll_configure_sr_hpm_lp()  argument
257 	clk_pll_configure(pll, regmap, config);  in clk_pll_configure_sr_hpm_lp()
259 		qcom_pll_set_fsm_mode(regmap, pll->mode_reg, 1, 0);  in clk_pll_configure_sr_hpm_lp()
269 	ret = regmap_read(pll->clkr.regmap, pll->mode_reg, &mode);  in clk_pll_sr2_enable()
274 	ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_BYPASSNL,  in clk_pll_sr2_enable()
286 	ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_RESET_N,  in clk_pll_sr2_enable()
296 	return regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_OUTCTRL,  in clk_pll_sr2_enable()
313 	regmap_read(pll->clkr.regmap, pll->mode_reg, &mode);  in clk_pll_sr2_set_rate()
319 	regmap_update_bits(pll->clkr.regmap, pll->l_reg, 0x3ff, f->l);  in clk_pll_sr2_set_rate()
320 	regmap_update_bits(pll->clkr.regmap, pll->m_reg, 0x7ffff, f->m);  in clk_pll_sr2_set_rate()
321 	regmap_update_bits(pll->clkr.regmap, pll->n_reg, 0x7ffff, f->n);  in clk_pll_sr2_set_rate()