Lines Matching +full:pll +full:-
1 // SPDX-License-Identifier: GPL-2.0
9 #include <linux/clk-provider.h>
13 #include "clk-alpha-pll.h"
16 #define PLL_MODE(p) ((p)->offset + 0x0)
36 #define PLL_L_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_L_VAL])
37 #define PLL_CAL_L_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_CAL_L_VAL])
38 #define PLL_ALPHA_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_ALPHA_VAL])
39 #define PLL_ALPHA_VAL_U(p) ((p)->offset + (p)->regs[PLL_OFF_ALPHA_VAL_U])
41 #define PLL_USER_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL])
43 # define PLL_POST_DIV_MASK(p) GENMASK((p)->width, 0)
49 #define PLL_USER_CTL_U(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL_U])
50 #define PLL_USER_CTL_U1(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL_U1])
52 #define PLL_CONFIG_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL])
53 #define PLL_CONFIG_CTL_U(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL_U])
54 #define PLL_CONFIG_CTL_U1(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL_U1])
55 #define PLL_TEST_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL])
56 #define PLL_TEST_CTL_U(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U])
57 #define PLL_TEST_CTL_U1(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U1])
58 #define PLL_STATUS(p) ((p)->offset + (p)->regs[PLL_OFF_STATUS])
59 #define PLL_OPMODE(p) ((p)->offset + (p)->regs[PLL_OFF_OPMODE])
60 #define PLL_FRAC(p) ((p)->offset + (p)->regs[PLL_OFF_FRAC])
214 /* TRION PLL specific settings and offsets */
218 /* LUCID PLL specific settings and offsets */
221 /* LUCID 5LPE PLL specific settings and offsets */
227 /* LUCID EVO PLL specific settings and offsets */
233 /* ZONDA PLL specific */
239 ((PLL_ALPHA_VAL_U(p) - PLL_ALPHA_VAL(p) == 4) ? \
242 #define pll_has_64bit_config(p) ((PLL_CONFIG_CTL_U(p) - PLL_CONFIG_CTL(p)) == 4)
250 static int wait_for_pll(struct clk_alpha_pll *pll, u32 mask, bool inverse, in wait_for_pll() argument
256 const char *name = clk_hw_get_name(&pll->clkr.hw); in wait_for_pll()
258 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); in wait_for_pll()
262 for (count = 200; count > 0; count--) { in wait_for_pll()
263 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); in wait_for_pll()
275 return -ETIMEDOUT; in wait_for_pll()
278 #define wait_for_pll_enable_active(pll) \ argument
279 wait_for_pll(pll, PLL_ACTIVE_FLAG, 0, "enable")
281 #define wait_for_pll_enable_lock(pll) \ argument
282 wait_for_pll(pll, PLL_LOCK_DET, 0, "enable")
284 #define wait_for_zonda_pll_freq_lock(pll) \ argument
285 wait_for_pll(pll, ZONDA_PLL_FREQ_LOCK_DET, 0, "freq enable")
287 #define wait_for_pll_disable(pll) \ argument
288 wait_for_pll(pll, PLL_ACTIVE_FLAG, 1, "disable")
290 #define wait_for_pll_offline(pll) \ argument
291 wait_for_pll(pll, PLL_OFFLINE_ACK, 0, "offline")
293 #define wait_for_pll_update(pll) \ argument
294 wait_for_pll(pll, PLL_UPDATE, 1, "update")
296 #define wait_for_pll_update_ack_set(pll) \ argument
297 wait_for_pll(pll, ALPHA_PLL_ACK_LATCH, 0, "update_ack_set")
299 #define wait_for_pll_update_ack_clear(pll) \ argument
300 wait_for_pll(pll, ALPHA_PLL_ACK_LATCH, 1, "update_ack_clear")
309 void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, in clk_alpha_pll_configure() argument
314 regmap_write(regmap, PLL_L_VAL(pll), config->l); in clk_alpha_pll_configure()
315 regmap_write(regmap, PLL_ALPHA_VAL(pll), config->alpha); in clk_alpha_pll_configure()
316 regmap_write(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); in clk_alpha_pll_configure()
318 if (pll_has_64bit_config(pll)) in clk_alpha_pll_configure()
319 regmap_write(regmap, PLL_CONFIG_CTL_U(pll), in clk_alpha_pll_configure()
320 config->config_ctl_hi_val); in clk_alpha_pll_configure()
322 if (pll_alpha_width(pll) > 32) in clk_alpha_pll_configure()
323 regmap_write(regmap, PLL_ALPHA_VAL_U(pll), config->alpha_hi); in clk_alpha_pll_configure()
325 val = config->main_output_mask; in clk_alpha_pll_configure()
326 val |= config->aux_output_mask; in clk_alpha_pll_configure()
327 val |= config->aux2_output_mask; in clk_alpha_pll_configure()
328 val |= config->early_output_mask; in clk_alpha_pll_configure()
329 val |= config->pre_div_val; in clk_alpha_pll_configure()
330 val |= config->post_div_val; in clk_alpha_pll_configure()
331 val |= config->vco_val; in clk_alpha_pll_configure()
332 val |= config->alpha_en_mask; in clk_alpha_pll_configure()
333 val |= config->alpha_mode_mask; in clk_alpha_pll_configure()
335 mask = config->main_output_mask; in clk_alpha_pll_configure()
336 mask |= config->aux_output_mask; in clk_alpha_pll_configure()
337 mask |= config->aux2_output_mask; in clk_alpha_pll_configure()
338 mask |= config->early_output_mask; in clk_alpha_pll_configure()
339 mask |= config->pre_div_mask; in clk_alpha_pll_configure()
340 mask |= config->post_div_mask; in clk_alpha_pll_configure()
341 mask |= config->vco_mask; in clk_alpha_pll_configure()
343 regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val); in clk_alpha_pll_configure()
345 if (pll->flags & SUPPORTS_FSM_MODE) in clk_alpha_pll_configure()
346 qcom_pll_set_fsm_mode(regmap, PLL_MODE(pll), 6, 0); in clk_alpha_pll_configure()
353 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_alpha_pll_hwfsm_enable() local
356 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); in clk_alpha_pll_hwfsm_enable()
362 if (pll->flags & SUPPORTS_OFFLINE_REQ) in clk_alpha_pll_hwfsm_enable()
365 ret = regmap_write(pll->clkr.regmap, PLL_MODE(pll), val); in clk_alpha_pll_hwfsm_enable()
372 return wait_for_pll_enable_active(pll); in clk_alpha_pll_hwfsm_enable()
378 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_alpha_pll_hwfsm_disable() local
381 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); in clk_alpha_pll_hwfsm_disable()
385 if (pll->flags & SUPPORTS_OFFLINE_REQ) { in clk_alpha_pll_hwfsm_disable()
386 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), in clk_alpha_pll_hwfsm_disable()
391 ret = wait_for_pll_offline(pll); in clk_alpha_pll_hwfsm_disable()
397 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), in clk_alpha_pll_hwfsm_disable()
402 wait_for_pll_disable(pll); in clk_alpha_pll_hwfsm_disable()
408 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in pll_is_enabled() local
411 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); in pll_is_enabled()
431 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_alpha_pll_enable() local
435 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); in clk_alpha_pll_enable()
444 return wait_for_pll_enable_active(pll); in clk_alpha_pll_enable()
451 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), in clk_alpha_pll_enable()
458 * de-asserting the reset. in clk_alpha_pll_enable()
463 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), in clk_alpha_pll_enable()
468 ret = wait_for_pll_enable_lock(pll); in clk_alpha_pll_enable()
472 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), in clk_alpha_pll_enable()
483 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_alpha_pll_disable() local
486 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); in clk_alpha_pll_disable()
497 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), mask, 0); in clk_alpha_pll_disable()
504 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), mask, 0); in clk_alpha_pll_disable()
542 alpha_pll_find_vco(const struct clk_alpha_pll *pll, unsigned long rate) in alpha_pll_find_vco() argument
544 const struct pll_vco *v = pll->vco_table; in alpha_pll_find_vco()
545 const struct pll_vco *end = v + pll->num_vco; in alpha_pll_find_vco()
548 if (rate >= v->min_freq && rate <= v->max_freq) in alpha_pll_find_vco()
559 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_alpha_pll_recalc_rate() local
560 u32 alpha_width = pll_alpha_width(pll); in clk_alpha_pll_recalc_rate()
562 regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l); in clk_alpha_pll_recalc_rate()
564 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl); in clk_alpha_pll_recalc_rate()
566 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &low); in clk_alpha_pll_recalc_rate()
568 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll), in clk_alpha_pll_recalc_rate()
572 a = low & GENMASK(alpha_width - 1, 0); in clk_alpha_pll_recalc_rate()
576 a >>= alpha_width - ALPHA_BITWIDTH; in clk_alpha_pll_recalc_rate()
583 static int __clk_alpha_pll_update_latch(struct clk_alpha_pll *pll) in __clk_alpha_pll_update_latch() argument
588 regmap_read(pll->clkr.regmap, PLL_MODE(pll), &mode); in __clk_alpha_pll_update_latch()
590 /* Latch the input to the PLL */ in __clk_alpha_pll_update_latch()
591 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_UPDATE, in __clk_alpha_pll_update_latch()
598 * PLL will latch the new L, Alpha and freq control word. in __clk_alpha_pll_update_latch()
599 * PLL will respond by raising PLL_ACK_LATCH output when new programming in __clk_alpha_pll_update_latch()
600 * has been latched in and PLL is being updated. When in __clk_alpha_pll_update_latch()
602 * automatically by hardware when PLL_ACK_LATCH is asserted by PLL. in __clk_alpha_pll_update_latch()
605 ret = wait_for_pll_update_ack_set(pll); in __clk_alpha_pll_update_latch()
609 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_UPDATE, 0); in __clk_alpha_pll_update_latch()
611 ret = wait_for_pll_update(pll); in __clk_alpha_pll_update_latch()
616 ret = wait_for_pll_update_ack_clear(pll); in __clk_alpha_pll_update_latch()
620 /* Wait for PLL output to stabilize */ in __clk_alpha_pll_update_latch()
626 static int clk_alpha_pll_update_latch(struct clk_alpha_pll *pll, in clk_alpha_pll_update_latch() argument
629 if (!is_enabled(&pll->clkr.hw) || in clk_alpha_pll_update_latch()
630 !(pll->flags & SUPPORTS_DYNAMIC_UPDATE)) in clk_alpha_pll_update_latch()
633 return __clk_alpha_pll_update_latch(pll); in clk_alpha_pll_update_latch()
640 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in __clk_alpha_pll_set_rate() local
642 u32 l, alpha_width = pll_alpha_width(pll); in __clk_alpha_pll_set_rate()
646 vco = alpha_pll_find_vco(pll, rate); in __clk_alpha_pll_set_rate()
647 if (pll->vco_table && !vco) { in __clk_alpha_pll_set_rate()
648 pr_err("%s: alpha pll not in a valid vco range\n", in __clk_alpha_pll_set_rate()
650 return -EINVAL; in __clk_alpha_pll_set_rate()
653 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); in __clk_alpha_pll_set_rate()
656 a <<= alpha_width - ALPHA_BITWIDTH; in __clk_alpha_pll_set_rate()
659 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll), a >> 32); in __clk_alpha_pll_set_rate()
661 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); in __clk_alpha_pll_set_rate()
664 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), in __clk_alpha_pll_set_rate()
666 vco->val << PLL_VCO_SHIFT); in __clk_alpha_pll_set_rate()
669 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), in __clk_alpha_pll_set_rate()
672 return clk_alpha_pll_update_latch(pll, is_enabled); in __clk_alpha_pll_set_rate()
692 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_alpha_pll_round_rate() local
693 u32 l, alpha_width = pll_alpha_width(pll); in clk_alpha_pll_round_rate()
698 if (!pll->vco_table || alpha_pll_find_vco(pll, rate)) in clk_alpha_pll_round_rate()
701 min_freq = pll->vco_table[0].min_freq; in clk_alpha_pll_round_rate()
702 max_freq = pll->vco_table[pll->num_vco - 1].max_freq; in clk_alpha_pll_round_rate()
712 * of [-0.5, 0.5). in alpha_huayra_pll_calc_rate()
714 if (a >= BIT(PLL_HUAYRA_ALPHA_WIDTH - 1)) in alpha_huayra_pll_calc_rate()
715 l -= 1; in alpha_huayra_pll_calc_rate()
744 * of [-0.5, 0.5) so if quotient >= 0.5 then increment the l value in alpha_huayra_pll_round_rate()
747 if (quotient >= BIT(PLL_HUAYRA_ALPHA_WIDTH - 1)) in alpha_huayra_pll_round_rate()
758 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in alpha_pll_huayra_recalc_rate() local
761 regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l); in alpha_pll_huayra_recalc_rate()
762 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl); in alpha_pll_huayra_recalc_rate()
765 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &alpha); in alpha_pll_huayra_recalc_rate()
773 * M is a signed number (-128 to 127) and N is unsigned in alpha_pll_huayra_recalc_rate()
774 * (0 to 255). M/N has to be within +/-0.5. in alpha_pll_huayra_recalc_rate()
777 * range [-0.5, 0.5). in alpha_pll_huayra_recalc_rate()
791 if (alpha_m >= BIT(PLL_HUAYRA_M_WIDTH - 1)) { in alpha_pll_huayra_recalc_rate()
792 alpha_m = BIT(PLL_HUAYRA_M_WIDTH) - alpha_m; in alpha_pll_huayra_recalc_rate()
795 rate -= tmp; in alpha_pll_huayra_recalc_rate()
811 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in alpha_pll_huayra_set_rate() local
816 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl); in alpha_pll_huayra_set_rate()
819 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &cur_alpha); in alpha_pll_huayra_set_rate()
822 * Huayra PLL supports PLL dynamic programming. User can change L_VAL, in alpha_pll_huayra_set_rate()
829 return -EBUSY; in alpha_pll_huayra_set_rate()
832 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); in alpha_pll_huayra_set_rate()
835 return wait_for_pll_enable_lock(pll); in alpha_pll_huayra_set_rate()
838 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); in alpha_pll_huayra_set_rate()
839 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); in alpha_pll_huayra_set_rate()
842 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), in alpha_pll_huayra_set_rate()
845 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), in alpha_pll_huayra_set_rate()
859 static int trion_pll_is_enabled(struct clk_alpha_pll *pll, in trion_pll_is_enabled() argument
865 ret = regmap_read(regmap, PLL_MODE(pll), &mode_val); in trion_pll_is_enabled()
866 ret |= regmap_read(regmap, PLL_OPMODE(pll), &opmode_val); in trion_pll_is_enabled()
875 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_trion_pll_is_enabled() local
877 return trion_pll_is_enabled(pll, pll->clkr.regmap); in clk_trion_pll_is_enabled()
882 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_trion_pll_enable() local
883 struct regmap *regmap = pll->clkr.regmap; in clk_trion_pll_enable()
887 ret = regmap_read(regmap, PLL_MODE(pll), &val); in clk_trion_pll_enable()
896 return wait_for_pll_enable_active(pll); in clk_trion_pll_enable()
900 regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN); in clk_trion_pll_enable()
902 ret = wait_for_pll_enable_lock(pll); in clk_trion_pll_enable()
906 /* Enable the PLL outputs */ in clk_trion_pll_enable()
907 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), in clk_trion_pll_enable()
912 /* Enable the global PLL outputs */ in clk_trion_pll_enable()
913 return regmap_update_bits(regmap, PLL_MODE(pll), in clk_trion_pll_enable()
919 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_trion_pll_disable() local
920 struct regmap *regmap = pll->clkr.regmap; in clk_trion_pll_disable()
924 ret = regmap_read(regmap, PLL_MODE(pll), &val); in clk_trion_pll_disable()
934 /* Disable the global PLL output */ in clk_trion_pll_disable()
935 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); in clk_trion_pll_disable()
939 /* Disable the PLL outputs */ in clk_trion_pll_disable()
940 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), in clk_trion_pll_disable()
945 /* Place the PLL mode in STANDBY */ in clk_trion_pll_disable()
946 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); in clk_trion_pll_disable()
947 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); in clk_trion_pll_disable()
953 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_trion_pll_recalc_rate() local
954 u32 l, frac, alpha_width = pll_alpha_width(pll); in clk_trion_pll_recalc_rate()
956 regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l); in clk_trion_pll_recalc_rate()
957 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &frac); in clk_trion_pll_recalc_rate()
1012 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); in clk_alpha_pll_postdiv_recalc_rate() local
1015 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl); in clk_alpha_pll_postdiv_recalc_rate()
1018 ctl &= PLL_POST_DIV_MASK(pll); in clk_alpha_pll_postdiv_recalc_rate()
1043 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); in clk_alpha_pll_postdiv_round_rate() local
1046 if (pll->width == 2) in clk_alpha_pll_postdiv_round_rate()
1052 pll->width, CLK_DIVIDER_POWER_OF_TWO); in clk_alpha_pll_postdiv_round_rate()
1059 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); in clk_alpha_pll_postdiv_round_ro_rate() local
1062 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl); in clk_alpha_pll_postdiv_round_ro_rate()
1065 ctl &= BIT(pll->width) - 1; in clk_alpha_pll_postdiv_round_ro_rate()
1077 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); in clk_alpha_pll_postdiv_set_rate() local
1080 /* 16 -> 0xf, 8 -> 0x7, 4 -> 0x3, 2 -> 0x1, 1 -> 0x0 */ in clk_alpha_pll_postdiv_set_rate()
1081 div = DIV_ROUND_UP_ULL(parent_rate, rate) - 1; in clk_alpha_pll_postdiv_set_rate()
1083 return regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), in clk_alpha_pll_postdiv_set_rate()
1084 PLL_POST_DIV_MASK(pll) << PLL_POST_DIV_SHIFT, in clk_alpha_pll_postdiv_set_rate()
1101 void clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, in clk_fabia_pll_configure() argument
1106 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); in clk_fabia_pll_configure()
1107 clk_alpha_pll_write_config(regmap, PLL_FRAC(pll), config->alpha); in clk_fabia_pll_configure()
1108 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), in clk_fabia_pll_configure()
1109 config->config_ctl_val); in clk_fabia_pll_configure()
1110 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), in clk_fabia_pll_configure()
1111 config->config_ctl_hi_val); in clk_fabia_pll_configure()
1112 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), in clk_fabia_pll_configure()
1113 config->user_ctl_val); in clk_fabia_pll_configure()
1114 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), in clk_fabia_pll_configure()
1115 config->user_ctl_hi_val); in clk_fabia_pll_configure()
1116 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), in clk_fabia_pll_configure()
1117 config->test_ctl_val); in clk_fabia_pll_configure()
1118 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), in clk_fabia_pll_configure()
1119 config->test_ctl_hi_val); in clk_fabia_pll_configure()
1121 if (config->post_div_mask) { in clk_fabia_pll_configure()
1122 mask = config->post_div_mask; in clk_fabia_pll_configure()
1123 val = config->post_div_val; in clk_fabia_pll_configure()
1124 regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val); in clk_fabia_pll_configure()
1127 if (pll->flags & SUPPORTS_FSM_LEGACY_MODE) in clk_fabia_pll_configure()
1128 regmap_update_bits(regmap, PLL_MODE(pll), PLL_FSM_LEGACY_MODE, in clk_fabia_pll_configure()
1131 regmap_update_bits(regmap, PLL_MODE(pll), PLL_UPDATE_BYPASS, in clk_fabia_pll_configure()
1134 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); in clk_fabia_pll_configure()
1141 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in alpha_pll_fabia_enable() local
1143 struct regmap *regmap = pll->clkr.regmap; in alpha_pll_fabia_enable()
1145 ret = regmap_read(regmap, PLL_MODE(pll), &val); in alpha_pll_fabia_enable()
1154 return wait_for_pll_enable_active(pll); in alpha_pll_fabia_enable()
1157 ret = regmap_read(regmap, PLL_OPMODE(pll), &opmode_val); in alpha_pll_fabia_enable()
1161 /* Skip If PLL is already running */ in alpha_pll_fabia_enable()
1165 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); in alpha_pll_fabia_enable()
1169 ret = regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); in alpha_pll_fabia_enable()
1173 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, in alpha_pll_fabia_enable()
1178 ret = regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN); in alpha_pll_fabia_enable()
1182 ret = wait_for_pll_enable_lock(pll); in alpha_pll_fabia_enable()
1186 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), in alpha_pll_fabia_enable()
1191 return regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, in alpha_pll_fabia_enable()
1198 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in alpha_pll_fabia_disable() local
1200 struct regmap *regmap = pll->clkr.regmap; in alpha_pll_fabia_disable()
1202 ret = regmap_read(regmap, PLL_MODE(pll), &val); in alpha_pll_fabia_disable()
1212 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); in alpha_pll_fabia_disable()
1217 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, 0); in alpha_pll_fabia_disable()
1221 /* Place the PLL in STANDBY */ in alpha_pll_fabia_disable()
1222 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); in alpha_pll_fabia_disable()
1228 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in alpha_pll_fabia_recalc_rate() local
1229 u32 l, frac, alpha_width = pll_alpha_width(pll); in alpha_pll_fabia_recalc_rate()
1231 regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l); in alpha_pll_fabia_recalc_rate()
1232 regmap_read(pll->clkr.regmap, PLL_FRAC(pll), &frac); in alpha_pll_fabia_recalc_rate()
1249 return -EINVAL; in alpha_pll_check_rate_margin()
1258 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in alpha_pll_fabia_set_rate() local
1259 u32 l, alpha_width = pll_alpha_width(pll); in alpha_pll_fabia_set_rate()
1270 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); in alpha_pll_fabia_set_rate()
1271 regmap_write(pll->clkr.regmap, PLL_FRAC(pll), a); in alpha_pll_fabia_set_rate()
1273 return __clk_alpha_pll_update_latch(pll); in alpha_pll_fabia_set_rate()
1278 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in alpha_pll_fabia_prepare() local
1282 u32 cal_l, val, alpha_width = pll_alpha_width(pll); in alpha_pll_fabia_prepare()
1287 /* Check if calibration needs to be done i.e. PLL is in reset */ in alpha_pll_fabia_prepare()
1288 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); in alpha_pll_fabia_prepare()
1296 vco = alpha_pll_find_vco(pll, clk_hw_get_rate(hw)); in alpha_pll_fabia_prepare()
1298 pr_err("%s: alpha pll not in a valid vco range\n", name); in alpha_pll_fabia_prepare()
1299 return -EINVAL; in alpha_pll_fabia_prepare()
1302 cal_freq = DIV_ROUND_CLOSEST((pll->vco_table[0].min_freq + in alpha_pll_fabia_prepare()
1303 pll->vco_table[0].max_freq) * 54, 100); in alpha_pll_fabia_prepare()
1307 return -EINVAL; in alpha_pll_fabia_prepare()
1316 /* Setup PLL for calibration frequency */ in alpha_pll_fabia_prepare()
1317 regmap_write(pll->clkr.regmap, PLL_CAL_L_VAL(pll), cal_l); in alpha_pll_fabia_prepare()
1319 /* Bringup the PLL at calibration frequency */ in alpha_pll_fabia_prepare()
1322 pr_err("%s: alpha pll calibration failed\n", name); in alpha_pll_fabia_prepare()
1354 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); in clk_alpha_pll_postdiv_fabia_recalc_rate() local
1358 ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val); in clk_alpha_pll_postdiv_fabia_recalc_rate()
1362 val >>= pll->post_div_shift; in clk_alpha_pll_postdiv_fabia_recalc_rate()
1363 val &= BIT(pll->width) - 1; in clk_alpha_pll_postdiv_fabia_recalc_rate()
1365 for (i = 0; i < pll->num_post_div; i++) { in clk_alpha_pll_postdiv_fabia_recalc_rate()
1366 if (pll->post_div_table[i].val == val) { in clk_alpha_pll_postdiv_fabia_recalc_rate()
1367 div = pll->post_div_table[i].div; in clk_alpha_pll_postdiv_fabia_recalc_rate()
1378 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); in clk_trion_pll_postdiv_recalc_rate() local
1379 struct regmap *regmap = pll->clkr.regmap; in clk_trion_pll_postdiv_recalc_rate()
1382 regmap_read(regmap, PLL_USER_CTL(pll), &val); in clk_trion_pll_postdiv_recalc_rate()
1384 val >>= pll->post_div_shift; in clk_trion_pll_postdiv_recalc_rate()
1385 val &= PLL_POST_DIV_MASK(pll); in clk_trion_pll_postdiv_recalc_rate()
1387 for (i = 0; i < pll->num_post_div; i++) { in clk_trion_pll_postdiv_recalc_rate()
1388 if (pll->post_div_table[i].val == val) { in clk_trion_pll_postdiv_recalc_rate()
1389 div = pll->post_div_table[i].div; in clk_trion_pll_postdiv_recalc_rate()
1401 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); in clk_trion_pll_postdiv_round_rate() local
1403 return divider_round_rate(hw, rate, prate, pll->post_div_table, in clk_trion_pll_postdiv_round_rate()
1404 pll->width, CLK_DIVIDER_ROUND_CLOSEST); in clk_trion_pll_postdiv_round_rate()
1411 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); in clk_trion_pll_postdiv_set_rate() local
1412 struct regmap *regmap = pll->clkr.regmap; in clk_trion_pll_postdiv_set_rate()
1416 for (i = 0; i < pll->num_post_div; i++) { in clk_trion_pll_postdiv_set_rate()
1417 if (pll->post_div_table[i].div == div) { in clk_trion_pll_postdiv_set_rate()
1418 val = pll->post_div_table[i].val; in clk_trion_pll_postdiv_set_rate()
1423 return regmap_update_bits(regmap, PLL_USER_CTL(pll), in clk_trion_pll_postdiv_set_rate()
1424 PLL_POST_DIV_MASK(pll) << PLL_POST_DIV_SHIFT, in clk_trion_pll_postdiv_set_rate()
1438 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); in clk_alpha_pll_postdiv_fabia_round_rate() local
1440 return divider_round_rate(hw, rate, prate, pll->post_div_table, in clk_alpha_pll_postdiv_fabia_round_rate()
1441 pll->width, CLK_DIVIDER_ROUND_CLOSEST); in clk_alpha_pll_postdiv_fabia_round_rate()
1447 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); in clk_alpha_pll_postdiv_fabia_set_rate() local
1451 * If the PLL is in FSM mode, then treat set_rate callback as a in clk_alpha_pll_postdiv_fabia_set_rate()
1452 * no-operation. in clk_alpha_pll_postdiv_fabia_set_rate()
1454 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); in clk_alpha_pll_postdiv_fabia_set_rate()
1462 for (i = 0; i < pll->num_post_div; i++) { in clk_alpha_pll_postdiv_fabia_set_rate()
1463 if (pll->post_div_table[i].div == div) { in clk_alpha_pll_postdiv_fabia_set_rate()
1464 val = pll->post_div_table[i].val; in clk_alpha_pll_postdiv_fabia_set_rate()
1469 return regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), in clk_alpha_pll_postdiv_fabia_set_rate()
1470 (BIT(pll->width) - 1) << pll->post_div_shift, in clk_alpha_pll_postdiv_fabia_set_rate()
1471 val << pll->post_div_shift); in clk_alpha_pll_postdiv_fabia_set_rate()
1482 * clk_trion_pll_configure - configure the trion pll
1484 * @pll: clk alpha pll
1486 * @config: configuration to apply for pll
1488 void clk_trion_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, in clk_trion_pll_configure() argument
1492 * If the bootloader left the PLL enabled it's likely that there are in clk_trion_pll_configure()
1493 * RCGs that will lock up if we disable the PLL below. in clk_trion_pll_configure()
1495 if (trion_pll_is_enabled(pll, regmap)) { in clk_trion_pll_configure()
1496 pr_debug("Trion PLL is already enabled, skipping configuration\n"); in clk_trion_pll_configure()
1500 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); in clk_trion_pll_configure()
1501 regmap_write(regmap, PLL_CAL_L_VAL(pll), TRION_PLL_CAL_VAL); in clk_trion_pll_configure()
1502 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha); in clk_trion_pll_configure()
1503 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), in clk_trion_pll_configure()
1504 config->config_ctl_val); in clk_trion_pll_configure()
1505 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), in clk_trion_pll_configure()
1506 config->config_ctl_hi_val); in clk_trion_pll_configure()
1507 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), in clk_trion_pll_configure()
1508 config->config_ctl_hi1_val); in clk_trion_pll_configure()
1509 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), in clk_trion_pll_configure()
1510 config->user_ctl_val); in clk_trion_pll_configure()
1511 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), in clk_trion_pll_configure()
1512 config->user_ctl_hi_val); in clk_trion_pll_configure()
1513 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U1(pll), in clk_trion_pll_configure()
1514 config->user_ctl_hi1_val); in clk_trion_pll_configure()
1515 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), in clk_trion_pll_configure()
1516 config->test_ctl_val); in clk_trion_pll_configure()
1517 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), in clk_trion_pll_configure()
1518 config->test_ctl_hi_val); in clk_trion_pll_configure()
1519 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), in clk_trion_pll_configure()
1520 config->test_ctl_hi1_val); in clk_trion_pll_configure()
1522 regmap_update_bits(regmap, PLL_MODE(pll), PLL_UPDATE_BYPASS, in clk_trion_pll_configure()
1525 /* Disable PLL output */ in clk_trion_pll_configure()
1526 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); in clk_trion_pll_configure()
1529 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); in clk_trion_pll_configure()
1531 /* Place the PLL in STANDBY mode */ in clk_trion_pll_configure()
1532 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); in clk_trion_pll_configure()
1537 * The TRION PLL requires a power-on self-calibration which happens when the
1538 * PLL comes out of reset. Calibrate in case it is not completed.
1542 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in __alpha_pll_trion_prepare() local
1547 regmap_read(pll->clkr.regmap, PLL_STATUS(pll), &val); in __alpha_pll_trion_prepare()
1572 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in __alpha_pll_trion_set_rate() local
1574 u32 val, l, alpha_width = pll_alpha_width(pll); in __alpha_pll_trion_set_rate()
1584 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); in __alpha_pll_trion_set_rate()
1585 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); in __alpha_pll_trion_set_rate()
1587 /* Latch the PLL input */ in __alpha_pll_trion_set_rate()
1588 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), latch_bit, latch_bit); in __alpha_pll_trion_set_rate()
1594 regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); in __alpha_pll_trion_set_rate()
1596 pr_err("Lucid PLL latch failed. Output may be unstable!\n"); in __alpha_pll_trion_set_rate()
1597 return -EINVAL; in __alpha_pll_trion_set_rate()
1601 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), latch_bit, 0); in __alpha_pll_trion_set_rate()
1606 ret = wait_for_pll_enable_lock(pll); in __alpha_pll_trion_set_rate()
1611 /* Wait for PLL output to stabilize */ in __alpha_pll_trion_set_rate()
1651 void clk_agera_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, in clk_agera_pll_configure() argument
1654 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); in clk_agera_pll_configure()
1655 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha); in clk_agera_pll_configure()
1656 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), in clk_agera_pll_configure()
1657 config->user_ctl_val); in clk_agera_pll_configure()
1658 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), in clk_agera_pll_configure()
1659 config->config_ctl_val); in clk_agera_pll_configure()
1660 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), in clk_agera_pll_configure()
1661 config->config_ctl_hi_val); in clk_agera_pll_configure()
1662 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), in clk_agera_pll_configure()
1663 config->test_ctl_val); in clk_agera_pll_configure()
1664 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), in clk_agera_pll_configure()
1665 config->test_ctl_hi_val); in clk_agera_pll_configure()
1672 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_alpha_pll_agera_set_rate() local
1673 u32 l, alpha_width = pll_alpha_width(pll); in clk_alpha_pll_agera_set_rate()
1684 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); in clk_alpha_pll_agera_set_rate()
1685 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); in clk_alpha_pll_agera_set_rate()
1688 return wait_for_pll_enable_lock(pll); in clk_alpha_pll_agera_set_rate()
1705 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in alpha_pll_lucid_5lpe_enable() local
1709 ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val); in alpha_pll_lucid_5lpe_enable()
1718 return wait_for_pll_enable_lock(pll); in alpha_pll_lucid_5lpe_enable()
1721 /* Check if PLL is already enabled, return if enabled */ in alpha_pll_lucid_5lpe_enable()
1722 ret = trion_pll_is_enabled(pll, pll->clkr.regmap); in alpha_pll_lucid_5lpe_enable()
1726 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); in alpha_pll_lucid_5lpe_enable()
1730 regmap_write(pll->clkr.regmap, PLL_OPMODE(pll), PLL_RUN); in alpha_pll_lucid_5lpe_enable()
1732 ret = wait_for_pll_enable_lock(pll); in alpha_pll_lucid_5lpe_enable()
1736 /* Enable the PLL outputs */ in alpha_pll_lucid_5lpe_enable()
1737 ret = regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, PLL_OUT_MASK); in alpha_pll_lucid_5lpe_enable()
1741 /* Enable the global PLL outputs */ in alpha_pll_lucid_5lpe_enable()
1742 return regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL); in alpha_pll_lucid_5lpe_enable()
1747 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in alpha_pll_lucid_5lpe_disable() local
1751 ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val); in alpha_pll_lucid_5lpe_disable()
1761 /* Disable the global PLL output */ in alpha_pll_lucid_5lpe_disable()
1762 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); in alpha_pll_lucid_5lpe_disable()
1766 /* Disable the PLL outputs */ in alpha_pll_lucid_5lpe_disable()
1767 ret = regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, 0); in alpha_pll_lucid_5lpe_disable()
1771 /* Place the PLL mode in STANDBY */ in alpha_pll_lucid_5lpe_disable()
1772 regmap_write(pll->clkr.regmap, PLL_OPMODE(pll), PLL_STANDBY); in alpha_pll_lucid_5lpe_disable()
1776 * The Lucid 5LPE PLL requires a power-on self-calibration which happens
1777 * when the PLL comes out of reset. Calibrate in case it is not completed.
1781 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in alpha_pll_lucid_5lpe_prepare() local
1787 regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); in alpha_pll_lucid_5lpe_prepare()
1793 return -EINVAL; in alpha_pll_lucid_5lpe_prepare()
1816 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); in __clk_lucid_pll_postdiv_set_rate() local
1817 struct regmap *regmap = pll->clkr.regmap; in __clk_lucid_pll_postdiv_set_rate()
1822 * If the PLL is in FSM mode, then treat set_rate callback as a in __clk_lucid_pll_postdiv_set_rate()
1823 * no-operation. in __clk_lucid_pll_postdiv_set_rate()
1825 ret = regmap_read(regmap, PLL_USER_CTL(pll), &val); in __clk_lucid_pll_postdiv_set_rate()
1832 if (!pll->post_div_table) { in __clk_lucid_pll_postdiv_set_rate()
1833 pr_err("Missing the post_div_table for the %s PLL\n", in __clk_lucid_pll_postdiv_set_rate()
1834 clk_hw_get_name(&pll->clkr.hw)); in __clk_lucid_pll_postdiv_set_rate()
1835 return -EINVAL; in __clk_lucid_pll_postdiv_set_rate()
1839 for (i = 0; i < pll->num_post_div; i++) { in __clk_lucid_pll_postdiv_set_rate()
1840 if (pll->post_div_table[i].div == div) { in __clk_lucid_pll_postdiv_set_rate()
1841 val = pll->post_div_table[i].val; in __clk_lucid_pll_postdiv_set_rate()
1846 mask = GENMASK(pll->width + pll->post_div_shift - 1, pll->post_div_shift); in __clk_lucid_pll_postdiv_set_rate()
1847 return regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), in __clk_lucid_pll_postdiv_set_rate()
1848 mask, val << pll->post_div_shift); in __clk_lucid_pll_postdiv_set_rate()
1884 void clk_zonda_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, in clk_zonda_pll_configure() argument
1887 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); in clk_zonda_pll_configure()
1888 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha); in clk_zonda_pll_configure()
1889 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); in clk_zonda_pll_configure()
1890 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val); in clk_zonda_pll_configure()
1891 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val); in clk_zonda_pll_configure()
1892 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val); in clk_zonda_pll_configure()
1893 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val); in clk_zonda_pll_configure()
1894 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U1(pll), config->user_ctl_hi1_val); in clk_zonda_pll_configure()
1895 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val); in clk_zonda_pll_configure()
1896 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val); in clk_zonda_pll_configure()
1897 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val); in clk_zonda_pll_configure()
1899 regmap_update_bits(regmap, PLL_MODE(pll), PLL_BYPASSNL, 0); in clk_zonda_pll_configure()
1901 /* Disable PLL output */ in clk_zonda_pll_configure()
1902 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); in clk_zonda_pll_configure()
1905 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); in clk_zonda_pll_configure()
1907 /* Place the PLL in STANDBY mode */ in clk_zonda_pll_configure()
1908 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); in clk_zonda_pll_configure()
1914 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_zonda_pll_enable() local
1915 struct regmap *regmap = pll->clkr.regmap; in clk_zonda_pll_enable()
1919 regmap_read(regmap, PLL_MODE(pll), &val); in clk_zonda_pll_enable()
1926 return wait_for_pll_enable_active(pll); in clk_zonda_pll_enable()
1929 /* Get the PLL out of bypass mode */ in clk_zonda_pll_enable()
1930 regmap_update_bits(regmap, PLL_MODE(pll), PLL_BYPASSNL, PLL_BYPASSNL); in clk_zonda_pll_enable()
1934 * de-asserting the reset. in clk_zonda_pll_enable()
1938 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); in clk_zonda_pll_enable()
1941 regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN); in clk_zonda_pll_enable()
1943 regmap_read(regmap, PLL_TEST_CTL(pll), &val); in clk_zonda_pll_enable()
1947 ret = wait_for_zonda_pll_freq_lock(pll); in clk_zonda_pll_enable()
1949 ret = wait_for_pll_enable_lock(pll); in clk_zonda_pll_enable()
1953 /* Enable the PLL outputs */ in clk_zonda_pll_enable()
1954 regmap_update_bits(regmap, PLL_USER_CTL(pll), ZONDA_PLL_OUT_MASK, ZONDA_PLL_OUT_MASK); in clk_zonda_pll_enable()
1956 /* Enable the global PLL outputs */ in clk_zonda_pll_enable()
1957 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL); in clk_zonda_pll_enable()
1964 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_zonda_pll_disable() local
1965 struct regmap *regmap = pll->clkr.regmap; in clk_zonda_pll_disable()
1968 regmap_read(regmap, PLL_MODE(pll), &val); in clk_zonda_pll_disable()
1976 /* Disable the global PLL output */ in clk_zonda_pll_disable()
1977 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); in clk_zonda_pll_disable()
1979 /* Disable the PLL outputs */ in clk_zonda_pll_disable()
1980 regmap_update_bits(regmap, PLL_USER_CTL(pll), ZONDA_PLL_OUT_MASK, 0); in clk_zonda_pll_disable()
1982 /* Put the PLL in bypass and reset */ in clk_zonda_pll_disable()
1983 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N | PLL_BYPASSNL, 0); in clk_zonda_pll_disable()
1985 /* Place the PLL mode in OFF state */ in clk_zonda_pll_disable()
1986 regmap_write(regmap, PLL_OPMODE(pll), 0x0); in clk_zonda_pll_disable()
1992 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_zonda_pll_set_rate() local
1995 u32 l, alpha_width = pll_alpha_width(pll); in clk_zonda_pll_set_rate()
2005 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); in clk_zonda_pll_set_rate()
2006 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); in clk_zonda_pll_set_rate()
2012 regmap_read(pll->clkr.regmap, PLL_TEST_CTL(pll), &test_ctl_val); in clk_zonda_pll_set_rate()
2016 ret = wait_for_zonda_pll_freq_lock(pll); in clk_zonda_pll_set_rate()
2018 ret = wait_for_pll_enable_lock(pll); in clk_zonda_pll_set_rate()
2022 /* Wait for PLL output to stabilize */ in clk_zonda_pll_set_rate()
2037 void clk_lucid_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, in clk_lucid_evo_pll_configure() argument
2040 u32 lval = config->l; in clk_lucid_evo_pll_configure()
2043 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), lval); in clk_lucid_evo_pll_configure()
2044 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha); in clk_lucid_evo_pll_configure()
2045 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); in clk_lucid_evo_pll_configure()
2046 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val); in clk_lucid_evo_pll_configure()
2047 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val); in clk_lucid_evo_pll_configure()
2048 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val); in clk_lucid_evo_pll_configure()
2049 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val); in clk_lucid_evo_pll_configure()
2050 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val); in clk_lucid_evo_pll_configure()
2051 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val); in clk_lucid_evo_pll_configure()
2052 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val); in clk_lucid_evo_pll_configure()
2054 /* Disable PLL output */ in clk_lucid_evo_pll_configure()
2055 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); in clk_lucid_evo_pll_configure()
2057 /* Set operation mode to STANDBY and de-assert the reset */ in clk_lucid_evo_pll_configure()
2058 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); in clk_lucid_evo_pll_configure()
2059 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); in clk_lucid_evo_pll_configure()
2065 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in alpha_pll_lucid_evo_enable() local
2066 struct regmap *regmap = pll->clkr.regmap; in alpha_pll_lucid_evo_enable()
2070 ret = regmap_read(regmap, PLL_USER_CTL(pll), &val); in alpha_pll_lucid_evo_enable()
2079 return wait_for_pll_enable_lock(pll); in alpha_pll_lucid_evo_enable()
2082 /* Check if PLL is already enabled */ in alpha_pll_lucid_evo_enable()
2083 ret = trion_pll_is_enabled(pll, regmap); in alpha_pll_lucid_evo_enable()
2087 pr_warn("%s PLL is already enabled\n", clk_hw_get_name(&pll->clkr.hw)); in alpha_pll_lucid_evo_enable()
2091 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); in alpha_pll_lucid_evo_enable()
2096 regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN); in alpha_pll_lucid_evo_enable()
2098 ret = wait_for_pll_enable_lock(pll); in alpha_pll_lucid_evo_enable()
2102 /* Enable the PLL outputs */ in alpha_pll_lucid_evo_enable()
2103 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, PLL_OUT_MASK); in alpha_pll_lucid_evo_enable()
2107 /* Enable the global PLL outputs */ in alpha_pll_lucid_evo_enable()
2108 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL); in alpha_pll_lucid_evo_enable()
2119 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in _alpha_pll_lucid_evo_disable() local
2120 struct regmap *regmap = pll->clkr.regmap; in _alpha_pll_lucid_evo_disable()
2124 ret = regmap_read(regmap, PLL_USER_CTL(pll), &val); in _alpha_pll_lucid_evo_disable()
2134 /* Disable the global PLL output */ in _alpha_pll_lucid_evo_disable()
2135 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); in _alpha_pll_lucid_evo_disable()
2139 /* Disable the PLL outputs */ in _alpha_pll_lucid_evo_disable()
2140 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, 0); in _alpha_pll_lucid_evo_disable()
2144 /* Place the PLL mode in STANDBY */ in _alpha_pll_lucid_evo_disable()
2145 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); in _alpha_pll_lucid_evo_disable()
2148 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, 0); in _alpha_pll_lucid_evo_disable()
2153 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in _alpha_pll_lucid_evo_prepare() local
2159 regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); in _alpha_pll_lucid_evo_prepare()
2165 return -EINVAL; in _alpha_pll_lucid_evo_prepare()
2199 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in alpha_pll_lucid_evo_recalc_rate() local
2200 struct regmap *regmap = pll->clkr.regmap; in alpha_pll_lucid_evo_recalc_rate()
2203 regmap_read(regmap, PLL_L_VAL(pll), &l); in alpha_pll_lucid_evo_recalc_rate()
2205 regmap_read(regmap, PLL_ALPHA_VAL(pll), &frac); in alpha_pll_lucid_evo_recalc_rate()
2207 return alpha_pll_calc_rate(parent_rate, l, frac, pll_alpha_width(pll)); in alpha_pll_lucid_evo_recalc_rate()
2254 void clk_rivian_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, in clk_rivian_evo_pll_configure() argument
2257 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); in clk_rivian_evo_pll_configure()
2258 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val); in clk_rivian_evo_pll_configure()
2259 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val); in clk_rivian_evo_pll_configure()
2260 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val); in clk_rivian_evo_pll_configure()
2261 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val); in clk_rivian_evo_pll_configure()
2262 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); in clk_rivian_evo_pll_configure()
2263 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val); in clk_rivian_evo_pll_configure()
2264 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val); in clk_rivian_evo_pll_configure()
2266 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); in clk_rivian_evo_pll_configure()
2268 regmap_update_bits(regmap, PLL_MODE(pll), in clk_rivian_evo_pll_configure()
2277 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_rivian_evo_pll_recalc_rate() local
2280 regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l); in clk_rivian_evo_pll_recalc_rate()
2288 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_rivian_evo_pll_round_rate() local
2294 if (!pll->vco_table || alpha_pll_find_vco(pll, rate)) in clk_rivian_evo_pll_round_rate()
2297 min_freq = pll->vco_table[0].min_freq; in clk_rivian_evo_pll_round_rate()
2298 max_freq = pll->vco_table[pll->num_vco - 1].max_freq; in clk_rivian_evo_pll_round_rate()