1 // SPDX-License-Identifier: GPL-2.0
3  * MVEBU Core divider clock
7  * Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
12 #include <linux/clk-provider.h>
23  * to configure one particular core divider clock. Those hardware
37  * array of core divider clock descriptors for this SoC, as well as
50  * This structure represents one core divider clock for the clock
51  * framework, and is dynamically allocated for each core divider clock
70 	{ .mask = 0x3f, .offset = 8, .fieldbit = 1 }, /* NAND clock */
74 	{ .mask = 0x0f, .offset = 6, .fieldbit = 27 }, /* NAND clock */
82 	const struct clk_corediv_soc_desc *soc_desc = corediv->soc_desc;  in clk_corediv_is_enabled()
83 	const struct clk_corediv_desc *desc = corediv->desc;  in clk_corediv_is_enabled()
84 	u32 enable_mask = BIT(desc->fieldbit) << soc_desc->enable_bit_offset;  in clk_corediv_is_enabled()
86 	return !!(readl(corediv->reg) & enable_mask);  in clk_corediv_is_enabled()
92 	const struct clk_corediv_soc_desc *soc_desc = corediv->soc_desc;  in clk_corediv_enable()
93 	const struct clk_corediv_desc *desc = corediv->desc;  in clk_corediv_enable()
97 	spin_lock_irqsave(&corediv->lock, flags);  in clk_corediv_enable()
99 	reg = readl(corediv->reg);  in clk_corediv_enable()
100 	reg |= (BIT(desc->fieldbit) << soc_desc->enable_bit_offset);  in clk_corediv_enable()
101 	writel(reg, corediv->reg);  in clk_corediv_enable()
103 	spin_unlock_irqrestore(&corediv->lock, flags);  in clk_corediv_enable()
111 	const struct clk_corediv_soc_desc *soc_desc = corediv->soc_desc;  in clk_corediv_disable()
112 	const struct clk_corediv_desc *desc = corediv->desc;  in clk_corediv_disable()
116 	spin_lock_irqsave(&corediv->lock, flags);  in clk_corediv_disable()
118 	reg = readl(corediv->reg);  in clk_corediv_disable()
119 	reg &= ~(BIT(desc->fieldbit) << soc_desc->enable_bit_offset);  in clk_corediv_disable()
120 	writel(reg, corediv->reg);  in clk_corediv_disable()
122 	spin_unlock_irqrestore(&corediv->lock, flags);  in clk_corediv_disable()
129 	const struct clk_corediv_soc_desc *soc_desc = corediv->soc_desc;  in clk_corediv_recalc_rate()
130 	const struct clk_corediv_desc *desc = corediv->desc;  in clk_corediv_recalc_rate()
131 	u32 reg, div;  in clk_corediv_recalc_rate()  local
133 	reg = readl(corediv->reg + soc_desc->ratio_offset);  in clk_corediv_recalc_rate()
134 	div = (reg >> desc->offset) & desc->mask;  in clk_corediv_recalc_rate()
135 	return parent_rate / div;  in clk_corediv_recalc_rate()
142 	u32 div;  in clk_corediv_round_rate()  local
144 	div = *parent_rate / rate;  in clk_corediv_round_rate()
145 	if (div < 4)  in clk_corediv_round_rate()
146 		div = 4;  in clk_corediv_round_rate()
147 	else if (div > 6)  in clk_corediv_round_rate()
148 		div = 8;  in clk_corediv_round_rate()
150 	return *parent_rate / div;  in clk_corediv_round_rate()
157 	const struct clk_corediv_soc_desc *soc_desc = corediv->soc_desc;  in clk_corediv_set_rate()
158 	const struct clk_corediv_desc *desc = corediv->desc;  in clk_corediv_set_rate()
160 	u32 reg, div;  in clk_corediv_set_rate()  local
162 	div = parent_rate / rate;  in clk_corediv_set_rate()
164 	spin_lock_irqsave(&corediv->lock, flags);  in clk_corediv_set_rate()
167 	reg = readl(corediv->reg + soc_desc->ratio_offset);  in clk_corediv_set_rate()
168 	reg &= ~(desc->mask << desc->offset);  in clk_corediv_set_rate()
169 	reg |= (div & desc->mask) << desc->offset;  in clk_corediv_set_rate()
170 	writel(reg, corediv->reg + soc_desc->ratio_offset);  in clk_corediv_set_rate()
172 	/* Set reload-force for this clock */  in clk_corediv_set_rate()
173 	reg = readl(corediv->reg) | BIT(desc->fieldbit);  in clk_corediv_set_rate()
174 	writel(reg, corediv->reg);  in clk_corediv_set_rate()
176 	/* Now trigger the clock update */  in clk_corediv_set_rate()
177 	reg = readl(corediv->reg) | soc_desc->ratio_reload;  in clk_corediv_set_rate()
178 	writel(reg, corediv->reg);  in clk_corediv_set_rate()
185 	reg &= ~(CORE_CLK_DIV_RATIO_MASK | soc_desc->ratio_reload);  in clk_corediv_set_rate()
186 	writel(reg, corediv->reg);  in clk_corediv_set_rate()
189 	spin_unlock_irqrestore(&corediv->lock, flags);  in clk_corediv_set_rate()
268 	clk_data.clk_num = soc_desc->ndescs;  in mvebu_corediv_clk_init()
270 	/* clks holds the clock array */  in mvebu_corediv_clk_init()
275 	/* corediv holds the clock specific array */  in mvebu_corediv_clk_init()
281 	spin_lock_init(&corediv->lock);  in mvebu_corediv_clk_init()
284 		of_property_read_string_index(node, "clock-output-names",  in mvebu_corediv_clk_init()
289 		init.ops = &soc_desc->ops;  in mvebu_corediv_clk_init()
293 		corediv[i].desc = soc_desc->descs + i;  in mvebu_corediv_clk_init()
315 CLK_OF_DECLARE(armada370_corediv_clk, "marvell,armada-370-corediv-clock",
322 CLK_OF_DECLARE(armada375_corediv_clk, "marvell,armada-375-corediv-clock",
329 CLK_OF_DECLARE(armada380_corediv_clk, "marvell,armada-380-corediv-clock",
336 CLK_OF_DECLARE(mv98dx3236_corediv_clk, "marvell,mv98dx3236-corediv-clock",