Lines Matching +full:cortex +full:- +full:m3
1 // SPDX-License-Identifier: GPL-2.0+
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
11 * TBG-A-P --| | | | | | ______
12 * TBG-B-P --| Mux |--| /div1 |--| /div2 |--| Gate |--> perip_clk
13 * TBG-A-S --| | | | | | |______|
14 * TBG-B-S --|_____| |_______| |_______|
20 #include <linux/clk-provider.h>
202 .parent_names = (const char *[]){ "TBG-A-P", \
203 "TBG-B-P", "TBG-A-S", "TBG-B-S"}, \
212 .parent_names = (const char *[]){ "TBG-A-P", \
213 "TBG-B-P", "TBG-A-S", "TBG-B-S"}, \
238 .parent_names = (const char *[]){ "TBG-A-P", \
239 "TBG-B-P", "TBG-A-S", "TBG-B-S"}, \
246 .parent_names = (const char *[]){ "TBG-A-P", \
247 "TBG-B-P", "TBG-A-S", "TBG-B-S"}, \
285 REF_CLK_GATE_DIV(ddr_phy, "TBG-A-S"),
344 div = get_div(double_div->reg1, double_div->shift1); in clk_double_div_recalc_rate()
345 div *= get_div(double_div->reg2, double_div->shift2); in clk_double_div_recalc_rate()
435 if (armada_3700_pm_dvfs_is_enabled(pm_cpu->nb_pm_base)) { in clk_pm_cpu_get_parent()
436 val = armada_3700_pm_dvfs_get_cpu_parent(pm_cpu->nb_pm_base); in clk_pm_cpu_get_parent()
438 val = readl(pm_cpu->reg_mux) >> pm_cpu->shift_mux; in clk_pm_cpu_get_parent()
439 val &= pm_cpu->mask_mux; in clk_pm_cpu_get_parent()
451 if (armada_3700_pm_dvfs_is_enabled(pm_cpu->nb_pm_base)) in clk_pm_cpu_recalc_rate()
452 div = armada_3700_pm_dvfs_get_cpu_div(pm_cpu->nb_pm_base); in clk_pm_cpu_recalc_rate()
454 div = get_div(pm_cpu->reg_div, pm_cpu->shift_div); in clk_pm_cpu_recalc_rate()
462 struct regmap *base = pm_cpu->nb_pm_base; in clk_pm_cpu_round_rate()
467 return -EINVAL; in clk_pm_cpu_round_rate()
488 return -EINVAL; in clk_pm_cpu_round_rate()
504 * frequency in-between. The sequence therefore becomes:
528 pm_cpu->l1_expiration = jiffies; in clk_pm_cpu_set_rate_wa()
530 pm_cpu->l1_expiration = jiffies + msecs_to_jiffies(20); in clk_pm_cpu_set_rate_wa()
545 if (pm_cpu->l1_expiration && time_is_before_eq_jiffies(pm_cpu->l1_expiration)) in clk_pm_cpu_set_rate_wa()
554 pm_cpu->l1_expiration = 0; in clk_pm_cpu_set_rate_wa()
561 struct regmap *base = pm_cpu->nb_pm_base; in clk_pm_cpu_set_rate()
567 return -EINVAL; in clk_pm_cpu_set_rate()
599 return -EINVAL; in clk_pm_cpu_set_rate()
610 { .compatible = "marvell,armada-3700-periph-clock-nb",
612 { .compatible = "marvell,armada-3700-periph-clock-sb",
625 if (data->mux_hw) { in armada_3700_add_composite_clk()
628 mux_hw = data->mux_hw; in armada_3700_add_composite_clk()
630 mux->lock = lock; in armada_3700_add_composite_clk()
631 mux_ops = mux_hw->init->ops; in armada_3700_add_composite_clk()
632 mux->reg = reg + (u64)mux->reg; in armada_3700_add_composite_clk()
635 if (data->gate_hw) { in armada_3700_add_composite_clk()
638 gate_hw = data->gate_hw; in armada_3700_add_composite_clk()
640 gate->lock = lock; in armada_3700_add_composite_clk()
641 gate_ops = gate_hw->init->ops; in armada_3700_add_composite_clk()
642 gate->reg = reg + (u64)gate->reg; in armada_3700_add_composite_clk()
643 gate->flags = CLK_GATE_SET_TO_DISABLE; in armada_3700_add_composite_clk()
646 if (data->rate_hw) { in armada_3700_add_composite_clk()
647 rate_hw = data->rate_hw; in armada_3700_add_composite_clk()
648 rate_ops = rate_hw->init->ops; in armada_3700_add_composite_clk()
649 if (data->is_double_div) { in armada_3700_add_composite_clk()
653 rate->reg1 = reg + (u64)rate->reg1; in armada_3700_add_composite_clk()
654 rate->reg2 = reg + (u64)rate->reg2; in armada_3700_add_composite_clk()
660 rate->reg = reg + (u64)rate->reg; in armada_3700_add_composite_clk()
661 for (clkt = rate->table; clkt->div; clkt++) in armada_3700_add_composite_clk()
663 rate->width = order_base_2(table_size); in armada_3700_add_composite_clk()
664 rate->lock = lock; in armada_3700_add_composite_clk()
668 if (data->muxrate_hw) { in armada_3700_add_composite_clk()
670 struct clk_hw *muxrate_hw = data->muxrate_hw; in armada_3700_add_composite_clk()
674 pmcpu_clk->reg_mux = reg + (u64)pmcpu_clk->reg_mux; in armada_3700_add_composite_clk()
675 pmcpu_clk->reg_div = reg + (u64)pmcpu_clk->reg_div; in armada_3700_add_composite_clk()
679 mux_ops = muxrate_hw->init->ops; in armada_3700_add_composite_clk()
680 rate_ops = muxrate_hw->init->ops; in armada_3700_add_composite_clk()
683 "marvell,armada-3700-nb-pm"); in armada_3700_add_composite_clk()
684 pmcpu_clk->nb_pm_base = map; in armada_3700_add_composite_clk()
687 *hw = clk_hw_register_composite(dev, data->name, data->parent_names, in armada_3700_add_composite_clk()
688 data->num_parents, mux_hw, in armada_3700_add_composite_clk()
699 data->tbg_sel = readl(data->reg + TBG_SEL); in armada_3700_periph_clock_suspend()
700 data->div_sel0 = readl(data->reg + DIV_SEL0); in armada_3700_periph_clock_suspend()
701 data->div_sel1 = readl(data->reg + DIV_SEL1); in armada_3700_periph_clock_suspend()
702 data->div_sel2 = readl(data->reg + DIV_SEL2); in armada_3700_periph_clock_suspend()
703 data->clk_sel = readl(data->reg + CLK_SEL); in armada_3700_periph_clock_suspend()
704 data->clk_dis = readl(data->reg + CLK_DIS); in armada_3700_periph_clock_suspend()
713 /* Follow the same order than what the Cortex-M3 does (ATF code) */ in armada_3700_periph_clock_resume()
714 writel(data->clk_dis, data->reg + CLK_DIS); in armada_3700_periph_clock_resume()
715 writel(data->div_sel0, data->reg + DIV_SEL0); in armada_3700_periph_clock_resume()
716 writel(data->div_sel1, data->reg + DIV_SEL1); in armada_3700_periph_clock_resume()
717 writel(data->div_sel2, data->reg + DIV_SEL2); in armada_3700_periph_clock_resume()
718 writel(data->tbg_sel, data->reg + TBG_SEL); in armada_3700_periph_clock_resume()
719 writel(data->clk_sel, data->reg + CLK_SEL); in armada_3700_periph_clock_resume()
732 struct device_node *np = pdev->dev.of_node; in armada_3700_periph_clock_probe()
734 struct device *dev = &pdev->dev; in armada_3700_periph_clock_probe()
740 return -ENODEV; in armada_3700_periph_clock_probe()
747 return -ENOMEM; in armada_3700_periph_clock_probe()
749 driver_data->hw_data = devm_kzalloc(dev, in armada_3700_periph_clock_probe()
750 struct_size(driver_data->hw_data, in armada_3700_periph_clock_probe()
753 if (!driver_data->hw_data) in armada_3700_periph_clock_probe()
754 return -ENOMEM; in armada_3700_periph_clock_probe()
755 driver_data->hw_data->num = num_periph; in armada_3700_periph_clock_probe()
758 driver_data->reg = devm_ioremap_resource(dev, res); in armada_3700_periph_clock_probe()
759 if (IS_ERR(driver_data->reg)) in armada_3700_periph_clock_probe()
760 return PTR_ERR(driver_data->reg); in armada_3700_periph_clock_probe()
762 spin_lock_init(&driver_data->lock); in armada_3700_periph_clock_probe()
765 struct clk_hw **hw = &driver_data->hw_data->hws[i]; in armada_3700_periph_clock_probe()
766 if (armada_3700_add_composite_clk(&data[i], driver_data->reg, in armada_3700_periph_clock_probe()
767 &driver_data->lock, dev, hw)) in armada_3700_periph_clock_probe()
773 driver_data->hw_data); in armada_3700_periph_clock_probe()
776 clk_hw_unregister(driver_data->hw_data->hws[i]); in armada_3700_periph_clock_probe()
787 struct clk_hw_onecell_data *hw_data = data->hw_data; in armada_3700_periph_clock_remove()
790 of_clk_del_provider(pdev->dev.of_node); in armada_3700_periph_clock_remove()
792 for (i = 0; i < hw_data->num; i++) in armada_3700_periph_clock_remove()
793 clk_hw_unregister(hw_data->hws[i]); in armada_3700_periph_clock_remove()
802 .name = "marvell-armada-3700-periph-clock",