Lines Matching +full:mmp2 +full:- +full:clock

1 // SPDX-License-Identifier: GPL-2.0-only
3 * mmp2 clock framework source file
19 #include <dt-bindings/clock/marvell,mmp2.h>
20 #include <dt-bindings/power/marvell,mmp2.h>
180 struct mmp_clk_unit *unit = &pxa_unit->unit; in mmp2_main_clk_init()
185 if (pxa_unit->model == CLK_MODEL_MMP3) { in mmp2_main_clk_init()
187 pxa_unit->mpmu_base, in mmp2_main_clk_init()
191 pxa_unit->mpmu_base, in mmp2_main_clk_init()
200 pxa_unit->mpmu_base + MPMU_UART_PLL, in mmp2_main_clk_init()
207 pxa_unit->mpmu_base + MPMU_I2S0_PLL, in mmp2_main_clk_init()
212 pxa_unit->mpmu_base + MPMU_I2S1_PLL, in mmp2_main_clk_init()
216 mmp_register_gate_clks(unit, mpmu_gate_clks, pxa_unit->mpmu_base, in mmp2_main_clk_init()
283 struct mmp_clk_unit *unit = &pxa_unit->unit; in mmp2_apb_periph_clk_init()
285 mmp_register_mux_clks(unit, apbc_mux_clks, pxa_unit->apbc_base, in mmp2_apb_periph_clk_init()
288 mmp_register_gate_clks(unit, apbc_gate_clks, pxa_unit->apbc_base, in mmp2_apb_periph_clk_init()
291 if (pxa_unit->model == CLK_MODEL_MMP3) { in mmp2_apb_periph_clk_init()
292 mmp_register_gate_clks(unit, mmp3_apbc_gate_clks, pxa_unit->apbc_base, in mmp2_apb_periph_clk_init()
396 struct mmp_clk_unit *unit = &pxa_unit->unit; in mmp2_axi_periph_clk_init()
398 sdh_mix_config.reg_info.reg_clk_ctrl = pxa_unit->apmu_base + APMU_SDH0; in mmp2_axi_periph_clk_init()
404 ccic0_mix_config.reg_info.reg_clk_ctrl = pxa_unit->apmu_base + APMU_CCIC0; in mmp2_axi_periph_clk_init()
411 ccic1_mix_config.reg_info.reg_clk_ctrl = pxa_unit->apmu_base + APMU_CCIC1; in mmp2_axi_periph_clk_init()
418 mmp_register_mux_clks(unit, apmu_mux_clks, pxa_unit->apmu_base, in mmp2_axi_periph_clk_init()
421 mmp_register_div_clks(unit, apmu_div_clks, pxa_unit->apmu_base, in mmp2_axi_periph_clk_init()
424 mmp_register_gate_clks(unit, apmu_gate_clks, pxa_unit->apmu_base, in mmp2_axi_periph_clk_init()
427 if (pxa_unit->model == CLK_MODEL_MMP3) { in mmp2_axi_periph_clk_init()
428 mmp_register_mux_clks(unit, mmp3_apmu_mux_clks, pxa_unit->apmu_base, in mmp2_axi_periph_clk_init()
431 mmp_register_div_clks(unit, mmp3_apmu_div_clks, pxa_unit->apmu_base, in mmp2_axi_periph_clk_init()
434 mmp_register_gate_clks(unit, mmp3_apmu_gate_clks, pxa_unit->apmu_base, in mmp2_axi_periph_clk_init()
440 pxa_unit->apmu_base + APMU_GPU, in mmp2_axi_periph_clk_init()
447 pxa_unit->apmu_base + APMU_GPU, in mmp2_axi_periph_clk_init()
451 mmp_register_gate_clks(unit, mmp2_apmu_gate_clks, pxa_unit->apmu_base, in mmp2_axi_periph_clk_init()
469 cells[i].reg = pxa_unit->apbc_base + apbc_gate_clks[i].offset; in mmp2_clk_reset_init()
481 if (pxa_unit->model == CLK_MODEL_MMP3) { in mmp2_pm_domain_init()
482 pxa_unit->pm_domains[MMP2_POWER_DOMAIN_GPU] in mmp2_pm_domain_init()
484 pxa_unit->apmu_base + APMU_GPU, in mmp2_pm_domain_init()
487 pxa_unit->pm_domains[MMP2_POWER_DOMAIN_GPU] in mmp2_pm_domain_init()
489 pxa_unit->apmu_base + APMU_GPU, in mmp2_pm_domain_init()
493 pxa_unit->pd_data.num_domains++; in mmp2_pm_domain_init()
495 pxa_unit->pm_domains[MMP2_POWER_DOMAIN_AUDIO] in mmp2_pm_domain_init()
497 pxa_unit->apmu_base + APMU_AUDIO, in mmp2_pm_domain_init()
499 pxa_unit->pd_data.num_domains++; in mmp2_pm_domain_init()
501 if (pxa_unit->model == CLK_MODEL_MMP3) { in mmp2_pm_domain_init()
502 pxa_unit->pm_domains[MMP3_POWER_DOMAIN_CAMERA] in mmp2_pm_domain_init()
504 pxa_unit->apmu_base + APMU_CAMERA, in mmp2_pm_domain_init()
506 pxa_unit->pd_data.num_domains++; in mmp2_pm_domain_init()
509 pxa_unit->pd_data.domains = pxa_unit->pm_domains; in mmp2_pm_domain_init()
510 of_genpd_add_provider_onecell(np, &pxa_unit->pd_data); in mmp2_pm_domain_init()
521 if (of_device_is_compatible(np, "marvell,mmp3-clock")) in mmp2_clk_init()
522 pxa_unit->model = CLK_MODEL_MMP3; in mmp2_clk_init()
524 pxa_unit->model = CLK_MODEL_MMP2; in mmp2_clk_init()
526 pxa_unit->mpmu_base = of_iomap(np, 0); in mmp2_clk_init()
527 if (!pxa_unit->mpmu_base) { in mmp2_clk_init()
532 pxa_unit->apmu_base = of_iomap(np, 1); in mmp2_clk_init()
533 if (!pxa_unit->apmu_base) { in mmp2_clk_init()
538 pxa_unit->apbc_base = of_iomap(np, 2); in mmp2_clk_init()
539 if (!pxa_unit->apbc_base) { in mmp2_clk_init()
546 mmp_clk_init(np, &pxa_unit->unit, MMP2_NR_CLKS); in mmp2_clk_init()
559 iounmap(pxa_unit->apmu_base); in mmp2_clk_init()
561 iounmap(pxa_unit->mpmu_base); in mmp2_clk_init()
566 CLK_OF_DECLARE(mmp2_clk, "marvell,mmp2-clock", mmp2_clk_init);
567 CLK_OF_DECLARE(mmp3_clk, "marvell,mmp3-clock", mmp2_clk_init);