Lines Matching +full:0 +full:x1b
25 #define APBC_RTC 0x0
26 #define APBC_TWSI0 0x4
27 #define APBC_TWSI1 0x8
28 #define APBC_TWSI2 0xc
29 #define APBC_TWSI3 0x10
30 #define APBC_TWSI4 0x7c
31 #define APBC_TWSI5 0x80
32 #define APBC_KPC 0x18
33 #define APBC_TIMER 0x24
34 #define APBC_UART0 0x2c
35 #define APBC_UART1 0x30
36 #define APBC_UART2 0x34
37 #define APBC_UART3 0x88
38 #define APBC_GPIO 0x38
39 #define APBC_PWM0 0x3c
40 #define APBC_PWM1 0x40
41 #define APBC_PWM2 0x44
42 #define APBC_PWM3 0x48
43 #define APBC_SSP0 0x50
44 #define APBC_SSP1 0x54
45 #define APBC_SSP2 0x58
46 #define APBC_SSP3 0x5c
47 #define APBC_THERMAL0 0x90
48 #define APBC_THERMAL1 0x98
49 #define APBC_THERMAL2 0x9c
50 #define APBC_THERMAL3 0xa0
51 #define APMU_SDH0 0x54
52 #define APMU_SDH1 0x58
53 #define APMU_SDH2 0xe8
54 #define APMU_SDH3 0xec
55 #define APMU_SDH4 0x15c
56 #define APMU_USB 0x5c
57 #define APMU_DISP0 0x4c
58 #define APMU_DISP1 0x110
59 #define APMU_CCIC0 0x50
60 #define APMU_CCIC1 0xf4
61 #define APMU_USBHSIC0 0xf8
62 #define APMU_USBHSIC1 0xfc
63 #define APMU_GPU 0xcc
64 #define APMU_AUDIO 0x10c
65 #define APMU_CAMERA 0x1fc
67 #define MPMU_FCCR 0x8
68 #define MPMU_POSR 0x10
69 #define MPMU_UART_PLL 0x14
70 #define MPMU_PLL2_CR 0x34
71 #define MPMU_I2S0_PLL 0x40
72 #define MPMU_I2S1_PLL 0x44
73 #define MPMU_ACGR 0x1024
75 #define MPMU_PLL3_CR 0x50
76 #define MPMU_PLL3_CTRL1 0x58
77 #define MPMU_PLL1_CTRL 0x5c
78 #define MPMU_PLL_DIFF_CTRL 0x68
79 #define MPMU_PLL2_CTRL1 0x414
97 {MMP2_CLK_CLK32, "clk32", NULL, 0, 32768},
98 {MMP2_CLK_VCTCXO, "vctcxo", NULL, 0, 26000000},
99 {MMP2_CLK_USB_PLL, "usb_pll", NULL, 0, 480000000},
100 {0, "i2s_pll", NULL, 0, 99666667},
104 {MMP2_CLK_PLL1, "pll1", 797330000, MPMU_FCCR, 0x4000, MPMU_POSR, 0},
105 {MMP2_CLK_PLL2, "pll2", 0, MPMU_PLL2_CR, 0x0300, MPMU_PLL2_CR, 10},
109 …{MMP2_CLK_PLL2, "pll1", 797330000, MPMU_FCCR, 0x4000, MPMU_POSR, 0, 26000000…
110 …{MMP2_CLK_PLL2, "pll2", 0, MPMU_PLL2_CR, 0x0300, MPMU_PLL2_CR, 10, 26000000…
111 …P3_CLK_PLL1_P, "pll1_p", 0, MPMU_PLL_DIFF_CTRL, 0x0010, 0, 0, 797330000, M…
112 …{MMP3_CLK_PLL2_P, "pll2_p", 0, MPMU_PLL_DIFF_CTRL, 0x0100, MPMU_PLL2_CR, 10, 26000000…
113 …{MMP3_CLK_PLL3, "pll3", 0, MPMU_PLL3_CR, 0x0300, MPMU_PLL3_CR, 10, 26000000…
117 {MMP2_CLK_PLL1_2, "pll1_2", "pll1", 1, 2, 0},
118 {MMP2_CLK_PLL1_4, "pll1_4", "pll1_2", 1, 2, 0},
119 {MMP2_CLK_PLL1_8, "pll1_8", "pll1_4", 1, 2, 0},
120 {MMP2_CLK_PLL1_16, "pll1_16", "pll1_8", 1, 2, 0},
121 {MMP2_CLK_PLL1_20, "pll1_20", "pll1_4", 1, 5, 0},
122 {MMP2_CLK_PLL1_3, "pll1_3", "pll1", 1, 3, 0},
123 {MMP2_CLK_PLL1_6, "pll1_6", "pll1_3", 1, 2, 0},
124 {MMP2_CLK_PLL1_12, "pll1_12", "pll1_6", 1, 2, 0},
125 {MMP2_CLK_PLL2_2, "pll2_2", "pll2", 1, 2, 0},
126 {MMP2_CLK_PLL2_4, "pll2_4", "pll2_2", 1, 2, 0},
127 {MMP2_CLK_PLL2_8, "pll2_8", "pll2_4", 1, 2, 0},
128 {MMP2_CLK_PLL2_16, "pll2_16", "pll2_8", 1, 2, 0},
129 {MMP2_CLK_PLL2_3, "pll2_3", "pll2", 1, 3, 0},
130 {MMP2_CLK_PLL2_6, "pll2_6", "pll2_3", 1, 2, 0},
131 {MMP2_CLK_PLL2_12, "pll2_12", "pll2_6", 1, 2, 0},
132 {MMP2_CLK_VCTCXO_2, "vctcxo_2", "vctcxo", 1, 2, 0},
133 {MMP2_CLK_VCTCXO_4, "vctcxo_4", "vctcxo_2", 1, 2, 0},
138 .num_mask = 0x1fff,
139 .den_mask = 0x1fff,
141 .den_shift = 0,
151 .num_mask = 0x7fff,
152 .den_mask = 0x1fff,
153 .num_shift = 0,
155 .enable_mask = 0xd0000000,
173 …{MMP2_CLK_I2S0, "i2s0_clk", "i2s0_pll", CLK_SET_RATE_PARENT, MPMU_ACGR, 0x200000, 0x200000, 0x0, 0…
174 …{MMP2_CLK_I2S1, "i2s1_clk", "i2s1_pll", CLK_SET_RATE_PARENT, MPMU_ACGR, 0x100000, 0x100000, 0x0, 0…
237 …{0, "uart0_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART0…
238 …{0, "uart1_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART1…
239 …{0, "uart2_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART2…
240 …{0, "uart3_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART3…
241 …{0, "ssp0_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP0, 4,…
242 …{0, "ssp1_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP1, 4,…
243 …{0, "ssp2_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP2, 4,…
244 …{0, "ssp3_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP3, 4,…
245 …{0, "timer_mux", timer_parent_names, ARRAY_SIZE(timer_parent_names), CLK_SET_RATE_PARENT, APBC_TIM…
249 …{MMP2_CLK_TWSI0, "twsi0_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_TWSI0, 0x7, 0x3, 0x0, 0, &reset_…
250 …{MMP2_CLK_TWSI1, "twsi1_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_TWSI1, 0x7, 0x3, 0x0, 0, &reset_…
251 …{MMP2_CLK_TWSI2, "twsi2_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_TWSI2, 0x7, 0x3, 0x0, 0, &reset_…
252 …{MMP2_CLK_TWSI3, "twsi3_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_TWSI3, 0x7, 0x3, 0x0, 0, &reset_…
253 …{MMP2_CLK_TWSI4, "twsi4_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_TWSI4, 0x7, 0x3, 0x0, 0, &reset_…
254 …{MMP2_CLK_TWSI5, "twsi5_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_TWSI5, 0x7, 0x3, 0x0, 0, &reset_…
255 …{MMP2_CLK_GPIO, "gpio_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_GPIO, 0x7, 0x3, 0x0, 0, &reset_loc…
256 …{MMP2_CLK_KPC, "kpc_clk", "clk32", CLK_SET_RATE_PARENT, APBC_KPC, 0x7, 0x3, 0x0, MMP_CLK_GATE_NEED…
257 …{MMP2_CLK_RTC, "rtc_clk", "clk32", CLK_SET_RATE_PARENT, APBC_RTC, 0x87, 0x83, 0x0, MMP_CLK_GATE_NE…
258 …{MMP2_CLK_PWM0, "pwm0_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM0, 0x7, 0x3, 0x0, 0, &reset_lo…
259 …{MMP2_CLK_PWM1, "pwm1_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM1, 0x7, 0x3, 0x0, 0, &reset_lo…
260 …{MMP2_CLK_PWM2, "pwm2_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM2, 0x7, 0x3, 0x0, 0, &reset_lo…
261 …{MMP2_CLK_PWM3, "pwm3_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM3, 0x7, 0x3, 0x0, 0, &reset_lo…
263 …{MMP2_CLK_UART0, "uart0_clk", "uart0_mux", CLK_SET_RATE_PARENT, APBC_UART0, 0x7, 0x3, 0x0, 0, &uar…
264 …{MMP2_CLK_UART1, "uart1_clk", "uart1_mux", CLK_SET_RATE_PARENT, APBC_UART1, 0x7, 0x3, 0x0, 0, &uar…
265 …{MMP2_CLK_UART2, "uart2_clk", "uart2_mux", CLK_SET_RATE_PARENT, APBC_UART2, 0x7, 0x3, 0x0, 0, &uar…
266 …{MMP2_CLK_UART3, "uart3_clk", "uart3_mux", CLK_SET_RATE_PARENT, APBC_UART3, 0x7, 0x3, 0x0, 0, &uar…
267 …{MMP2_CLK_SSP0, "ssp0_clk", "ssp0_mux", CLK_SET_RATE_PARENT, APBC_SSP0, 0x7, 0x3, 0x0, 0, &ssp0_lo…
268 …{MMP2_CLK_SSP1, "ssp1_clk", "ssp1_mux", CLK_SET_RATE_PARENT, APBC_SSP1, 0x7, 0x3, 0x0, 0, &ssp1_lo…
269 …{MMP2_CLK_SSP2, "ssp2_clk", "ssp2_mux", CLK_SET_RATE_PARENT, APBC_SSP2, 0x7, 0x3, 0x0, 0, &ssp2_lo…
270 …{MMP2_CLK_SSP3, "ssp3_clk", "ssp3_mux", CLK_SET_RATE_PARENT, APBC_SSP3, 0x7, 0x3, 0x0, 0, &ssp3_lo…
271 …{MMP2_CLK_TIMER, "timer_clk", "timer_mux", CLK_SET_RATE_PARENT, APBC_TIMER, 0x7, 0x3, 0x0, 0, &tim…
272 …{MMP2_CLK_THERMAL0, "thermal0_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_THERMAL0, 0x7, 0x3, 0x0, M…
276 …{MMP3_CLK_THERMAL1, "thermal1_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_THERMAL1, 0x7, 0x3, 0x0, M…
277 …{MMP3_CLK_THERMAL2, "thermal2_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_THERMAL2, 0x7, 0x3, 0x0, M…
278 …{MMP3_CLK_THERMAL3, "thermal3_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_THERMAL3, 0x7, 0x3, 0x0, M…
317 static const u32 mmp2_gpu_gc_parent_table[] = { 0x0000, 0x0040, 0x0080, 0x00c0, 0x1000, 0x1…
319 static const u32 mmp2_gpu_bus_parent_table[] = { 0x0000, 0x0020, 0x0030, 0x4020 };
333 …arent_names, ARRAY_SIZE(disp_parent_names), CLK_SET_RATE_PARENT, APMU_DISP0, 6, 2, 0, &disp0_lock},
334 …arent_names, ARRAY_SIZE(disp_parent_names), CLK_SET_RATE_PARENT, APMU_DISP1, 6, 2, 0, &disp1_lock},
338 {0, "gpu_bus_mux", mmp3_gpu_bus_parent_names, ARRAY_SIZE(mmp3_gpu_bus_parent_names),
339 CLK_SET_RATE_PARENT, APMU_GPU, 4, 2, 0, &gpu_lock},
340 {0, "gpu_3d_mux", mmp3_gpu_gc_parent_names, ARRAY_SIZE(mmp3_gpu_gc_parent_names),
341 CLK_SET_RATE_PARENT, APMU_GPU, 6, 2, 0, &gpu_lock},
342 {0, "gpu_2d_mux", mmp3_gpu_gc_parent_names, ARRAY_SIZE(mmp3_gpu_gc_parent_names),
343 CLK_SET_RATE_PARENT, APMU_GPU, 12, 2, 0, &gpu_lock},
347 …{0, "disp0_div", "disp0_mux", CLK_SET_RATE_PARENT, APMU_DISP0, 8, 4, CLK_DIVIDER_ONE_BASED, &disp0…
348 {0, "disp0_sphy_div", "disp0_mux", CLK_SET_RATE_PARENT, APMU_DISP0, 15, 5, 0, &disp0_lock},
349 …{0, "disp1_div", "disp1_mux", CLK_SET_RATE_PARENT, APMU_DISP1, 8, 4, CLK_DIVIDER_ONE_BASED, &disp1…
350 {0, "ccic0_sphy_div", "ccic0_mix_clk", CLK_SET_RATE_PARENT, APMU_CCIC0, 10, 5, 0, &ccic0_lock},
351 {0, "ccic1_sphy_div", "ccic1_mix_clk", CLK_SET_RATE_PARENT, APMU_CCIC1, 10, 5, 0, &ccic1_lock},
355 {0, "gpu_3d_div", "gpu_3d_mux", CLK_SET_RATE_PARENT, APMU_GPU, 24, 4, 0, &gpu_lock},
356 {0, "gpu_2d_div", "gpu_2d_mux", CLK_SET_RATE_PARENT, APMU_GPU, 28, 4, 0, &gpu_lock},
360 {MMP2_CLK_USB, "usb_clk", "usb_pll", 0, APMU_USB, 0x9, 0x9, 0x0, 0, &usb_lock},
361 …{MMP2_CLK_USBHSIC0, "usbhsic0_clk", "usb_pll", 0, APMU_USBHSIC0, 0x1b, 0x1b, 0x0, 0, &usbhsic0_loc…
362 …{MMP2_CLK_USBHSIC1, "usbhsic1_clk", "usb_pll", 0, APMU_USBHSIC1, 0x1b, 0x1b, 0x0, 0, &usbhsic1_loc…
364 …{MMP2_CLK_SDH0, "sdh0_clk", "sdh_mix_clk", CLK_SET_RATE_PARENT, APMU_SDH0, 0x1b, 0x1b, 0x0, 0, &sd…
365 …{MMP2_CLK_SDH1, "sdh1_clk", "sdh_mix_clk", CLK_SET_RATE_PARENT, APMU_SDH1, 0x1b, 0x1b, 0x0, 0, &sd…
366 …{MMP2_CLK_SDH2, "sdh2_clk", "sdh_mix_clk", CLK_SET_RATE_PARENT, APMU_SDH2, 0x1b, 0x1b, 0x0, 0, &sd…
367 …{MMP2_CLK_SDH3, "sdh3_clk", "sdh_mix_clk", CLK_SET_RATE_PARENT, APMU_SDH3, 0x1b, 0x1b, 0x0, 0, &sd…
368 …{MMP2_CLK_DISP0, "disp0_clk", "disp0_div", CLK_SET_RATE_PARENT, APMU_DISP0, 0x12, 0x12, 0x0, 0, &d…
369 …C, "disp0_lcdc_clk", "disp0_mux", CLK_SET_RATE_PARENT, APMU_DISP0, 0x09, 0x09, 0x0, 0, &disp0_lock…
370 …p0_sphy_clk", "disp0_sphy_div", CLK_SET_RATE_PARENT, APMU_DISP0, 0x1024, 0x1024, 0x0, 0, &disp0_lo…
371 …{MMP2_CLK_DISP1, "disp1_clk", "disp1_div", CLK_SET_RATE_PARENT, APMU_DISP1, 0x09, 0x09, 0x0, 0, &d…
372 …ITER, "ccic_arbiter", "vctcxo", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x1800, 0x1800, 0x0, 0, &ccic0_lo…
373 …{MMP2_CLK_CCIC0, "ccic0_clk", "ccic0_mix_clk", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x1b, 0x1b, 0x0, 0…
374 …"ccic0_phy_clk", "ccic0_mix_clk", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x24, 0x24, 0x0, 0, &ccic0_lock…
375 …ic0_sphy_clk", "ccic0_sphy_div", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x300, 0x300, 0x0, 0, &ccic0_loc…
376 …{MMP2_CLK_CCIC1, "ccic1_clk", "ccic1_mix_clk", CLK_SET_RATE_PARENT, APMU_CCIC1, 0x1b, 0x1b, 0x0, 0…
377 …"ccic1_phy_clk", "ccic1_mix_clk", CLK_SET_RATE_PARENT, APMU_CCIC1, 0x24, 0x24, 0x0, 0, &ccic1_lock…
378 …ic1_sphy_clk", "ccic1_sphy_div", CLK_SET_RATE_PARENT, APMU_CCIC1, 0x300, 0x300, 0x0, 0, &ccic1_loc…
379 …{MMP2_CLK_GPU_BUS, "gpu_bus_clk", "gpu_bus_mux", CLK_SET_RATE_PARENT, APMU_GPU, 0xa, 0xa, 0x0, MMP…
380 …{MMP2_CLK_AUDIO, "audio_clk", "audio_mix_clk", CLK_SET_RATE_PARENT, APMU_AUDIO, 0x12, 0x12, 0x0, 0…
384 …{MMP2_CLK_GPU_3D, "gpu_3d_clk", "gpu_3d_mux", CLK_SET_RATE_PARENT, APMU_GPU, 0x5, 0x5, 0x0, MMP_CL…
388 …{MMP3_CLK_SDH4, "sdh4_clk", "sdh_mix_clk", CLK_SET_RATE_PARENT, APMU_SDH4, 0x1b, 0x1b, 0x0, 0, &sd…
389 …{MMP3_CLK_GPU_3D, "gpu_3d_clk", "gpu_3d_div", CLK_SET_RATE_PARENT, APMU_GPU, 0x5, 0x5, 0x0, MMP_CL…
390 …{MMP3_CLK_GPU_2D, "gpu_2d_clk", "gpu_2d_div", CLK_SET_RATE_PARENT, APMU_GPU, 0x1c0000, 0x1c0000, 0…
441 0, 0x10c0, 0, in mmp2_axi_periph_clk_init()
448 0, 0x4030, 0, in mmp2_axi_periph_clk_init()
467 for (i = 0; i < nr_resets; i++) { in mmp2_clk_reset_init()
470 cells[i].flags = 0; in mmp2_clk_reset_init()
472 cells[i].bits = 0x4; in mmp2_clk_reset_init()
485 0x0600, 0x40003, 0x18000c, 0, &gpu_lock); in mmp2_pm_domain_init()
490 0x8600, 0x00003, 0x00000c, in mmp2_pm_domain_init()
498 0x600, 0x2, 0, 0, &audio_lock); in mmp2_pm_domain_init()
505 0x600, 0, 0, 0, NULL); in mmp2_pm_domain_init()
526 pxa_unit->mpmu_base = of_iomap(np, 0); in mmp2_clk_init()