Lines Matching +full:0 +full:x1b
20 #define APBC_RTC 0x0
21 #define APBC_TWSI0 0x4
22 #define APBC_TWSI1 0x8
23 #define APBC_TWSI2 0xc
24 #define APBC_TWSI3 0x10
25 #define APBC_TWSI4 0x7c
26 #define APBC_TWSI5 0x80
27 #define APBC_KPC 0x18
28 #define APBC_UART0 0x2c
29 #define APBC_UART1 0x30
30 #define APBC_UART2 0x34
31 #define APBC_UART3 0x88
32 #define APBC_GPIO 0x38
33 #define APBC_PWM0 0x3c
34 #define APBC_PWM1 0x40
35 #define APBC_PWM2 0x44
36 #define APBC_PWM3 0x48
37 #define APBC_SSP0 0x50
38 #define APBC_SSP1 0x54
39 #define APBC_SSP2 0x58
40 #define APBC_SSP3 0x5c
41 #define APMU_SDH0 0x54
42 #define APMU_SDH1 0x58
43 #define APMU_SDH2 0xe8
44 #define APMU_SDH3 0xec
45 #define APMU_USB 0x5c
46 #define APMU_DISP0 0x4c
47 #define APMU_DISP1 0x110
48 #define APMU_CCIC0 0x50
49 #define APMU_CCIC1 0xf4
50 #define MPMU_UART_PLL 0x14
56 .num_mask = 0x1fff,
57 .den_mask = 0x1fff,
59 .den_shift = 0,
100 clk = clk_register_fixed_rate(NULL, "clk32", NULL, 0, 3200); in mmp2_clk_init()
103 vctcxo = clk_register_fixed_rate(NULL, "vctcxo", NULL, 0, 26000000); in mmp2_clk_init()
106 clk = clk_register_fixed_rate(NULL, "pll1", NULL, 0, 800000000); in mmp2_clk_init()
109 clk = clk_register_fixed_rate(NULL, "usb_pll", NULL, 0, 480000000); in mmp2_clk_init()
112 clk = clk_register_fixed_rate(NULL, "pll2", NULL, 0, 960000000); in mmp2_clk_init()
183 clk = mmp_clk_register_factor("uart_pll", "pll1_4", 0, in mmp2_clk_init()
191 apbc_base + APBC_TWSI0, 10, 0, &clk_lock); in mmp2_clk_init()
192 clk_register_clkdev(clk, NULL, "pxa2xx-i2c.0"); in mmp2_clk_init()
195 apbc_base + APBC_TWSI1, 10, 0, &clk_lock); in mmp2_clk_init()
199 apbc_base + APBC_TWSI2, 10, 0, &clk_lock); in mmp2_clk_init()
203 apbc_base + APBC_TWSI3, 10, 0, &clk_lock); in mmp2_clk_init()
207 apbc_base + APBC_TWSI4, 10, 0, &clk_lock); in mmp2_clk_init()
211 apbc_base + APBC_TWSI5, 10, 0, &clk_lock); in mmp2_clk_init()
215 apbc_base + APBC_GPIO, 10, 0, &clk_lock); in mmp2_clk_init()
219 apbc_base + APBC_KPC, 10, 0, &clk_lock); in mmp2_clk_init()
223 apbc_base + APBC_RTC, 10, 0, &clk_lock); in mmp2_clk_init()
227 apbc_base + APBC_PWM0, 10, 0, &clk_lock); in mmp2_clk_init()
228 clk_register_clkdev(clk, NULL, "mmp2-pwm.0"); in mmp2_clk_init()
231 apbc_base + APBC_PWM1, 10, 0, &clk_lock); in mmp2_clk_init()
235 apbc_base + APBC_PWM2, 10, 0, &clk_lock); in mmp2_clk_init()
239 apbc_base + APBC_PWM3, 10, 0, &clk_lock); in mmp2_clk_init()
245 apbc_base + APBC_UART0, 4, 3, 0, &clk_lock); in mmp2_clk_init()
247 clk_register_clkdev(clk, "uart_mux.0", NULL); in mmp2_clk_init()
250 apbc_base + APBC_UART0, 10, 0, &clk_lock); in mmp2_clk_init()
251 clk_register_clkdev(clk, NULL, "pxa2xx-uart.0"); in mmp2_clk_init()
256 apbc_base + APBC_UART1, 4, 3, 0, &clk_lock); in mmp2_clk_init()
261 apbc_base + APBC_UART1, 10, 0, &clk_lock); in mmp2_clk_init()
267 apbc_base + APBC_UART2, 4, 3, 0, &clk_lock); in mmp2_clk_init()
272 apbc_base + APBC_UART2, 10, 0, &clk_lock); in mmp2_clk_init()
278 apbc_base + APBC_UART3, 4, 3, 0, &clk_lock); in mmp2_clk_init()
283 apbc_base + APBC_UART3, 10, 0, &clk_lock); in mmp2_clk_init()
289 apbc_base + APBC_SSP0, 4, 3, 0, &clk_lock); in mmp2_clk_init()
290 clk_register_clkdev(clk, "uart_mux.0", NULL); in mmp2_clk_init()
293 apbc_base + APBC_SSP0, 10, 0, &clk_lock); in mmp2_clk_init()
294 clk_register_clkdev(clk, NULL, "mmp-ssp.0"); in mmp2_clk_init()
299 apbc_base + APBC_SSP1, 4, 3, 0, &clk_lock); in mmp2_clk_init()
303 apbc_base + APBC_SSP1, 10, 0, &clk_lock); in mmp2_clk_init()
309 apbc_base + APBC_SSP2, 4, 3, 0, &clk_lock); in mmp2_clk_init()
313 apbc_base + APBC_SSP2, 10, 0, &clk_lock); in mmp2_clk_init()
319 apbc_base + APBC_SSP3, 4, 3, 0, &clk_lock); in mmp2_clk_init()
323 apbc_base + APBC_SSP3, 10, 0, &clk_lock); in mmp2_clk_init()
329 apmu_base + APMU_SDH0, 8, 2, 0, &clk_lock); in mmp2_clk_init()
338 0x1b, &clk_lock); in mmp2_clk_init()
339 clk_register_clkdev(clk, NULL, "sdhci-pxav3.0"); in mmp2_clk_init()
342 0x1b, &clk_lock); in mmp2_clk_init()
346 0x1b, &clk_lock); in mmp2_clk_init()
350 0x1b, &clk_lock); in mmp2_clk_init()
354 0x9, &clk_lock); in mmp2_clk_init()
360 apmu_base + APMU_DISP0, 6, 2, 0, &clk_lock); in mmp2_clk_init()
361 clk_register_clkdev(clk, "disp_mux.0", NULL); in mmp2_clk_init()
366 clk_register_clkdev(clk, "disp_div.0", NULL); in mmp2_clk_init()
369 apmu_base + APMU_DISP0, 0x1b, &clk_lock); in mmp2_clk_init()
370 clk_register_clkdev(clk, NULL, "mmp-disp.0"); in mmp2_clk_init()
372 clk = clk_register_divider(NULL, "disp0_sphy_div", "disp0_mux", 0, in mmp2_clk_init()
373 apmu_base + APMU_DISP0, 15, 5, 0, &clk_lock); in mmp2_clk_init()
374 clk_register_clkdev(clk, "disp_sphy_div.0", NULL); in mmp2_clk_init()
377 apmu_base + APMU_DISP0, 0x1024, &clk_lock); in mmp2_clk_init()
378 clk_register_clkdev(clk, "disp_sphy.0", NULL); in mmp2_clk_init()
383 apmu_base + APMU_DISP1, 6, 2, 0, &clk_lock); in mmp2_clk_init()
392 apmu_base + APMU_DISP1, 0x1b, &clk_lock); in mmp2_clk_init()
396 apmu_base + APMU_CCIC0, 0x1800, &clk_lock); in mmp2_clk_init()
402 apmu_base + APMU_CCIC0, 6, 2, 0, &clk_lock); in mmp2_clk_init()
403 clk_register_clkdev(clk, "ccic_mux.0", NULL); in mmp2_clk_init()
408 clk_register_clkdev(clk, "ccic_div.0", NULL); in mmp2_clk_init()
411 apmu_base + APMU_CCIC0, 0x1b, &clk_lock); in mmp2_clk_init()
412 clk_register_clkdev(clk, "fnclk", "mmp-ccic.0"); in mmp2_clk_init()
415 apmu_base + APMU_CCIC0, 0x24, &clk_lock); in mmp2_clk_init()
416 clk_register_clkdev(clk, "phyclk", "mmp-ccic.0"); in mmp2_clk_init()
420 10, 5, 0, &clk_lock); in mmp2_clk_init()
421 clk_register_clkdev(clk, "sphyclk_div", "mmp-ccic.0"); in mmp2_clk_init()
424 apmu_base + APMU_CCIC0, 0x300, &clk_lock); in mmp2_clk_init()
425 clk_register_clkdev(clk, "sphyclk", "mmp-ccic.0"); in mmp2_clk_init()
430 apmu_base + APMU_CCIC1, 6, 2, 0, &clk_lock); in mmp2_clk_init()
439 apmu_base + APMU_CCIC1, 0x1b, &clk_lock); in mmp2_clk_init()
443 apmu_base + APMU_CCIC1, 0x24, &clk_lock); in mmp2_clk_init()
448 10, 5, 0, &clk_lock); in mmp2_clk_init()
452 apmu_base + APMU_CCIC1, 0x300, &clk_lock); in mmp2_clk_init()