1 // SPDX-License-Identifier: GPL-2.0-only
7 #include "asm-generic/errno-base.h"
8 #include <linux/clk-provider.h>
12 #include <dt-bindings/clock/microchip,mpfs-clock.h>
76 	void __iomem *mult_addr = ccc_hw->base + ccc_hw->reg_offset;  in mpfs_ccc_pll_recalc_rate()
77 	void __iomem *ref_div_addr = ccc_hw->base + MPFS_CCC_REF_CR;  in mpfs_ccc_pll_recalc_rate()
91 	void __iomem *pll_cr_addr = ccc_hw->base + MPFS_CCC_PLL_CR;  in mpfs_ccc_pll_get_parent()
169 		snprintf(name, 23, "%s_out%u", parent->name, i);  in mpfs_ccc_register_outputs()
170 		out_hw->divider.hw.init = CLK_HW_INIT_HW(name, &parent->hw, &clk_divider_ops, 0);  in mpfs_ccc_register_outputs()
171 		out_hw->divider.reg = data->pll_base[i / MPFS_CCC_OUTPUTS_PER_PLL] +  in mpfs_ccc_register_outputs()
172 			out_hw->reg_offset;  in mpfs_ccc_register_outputs()
174 		ret = devm_clk_hw_register(dev, &out_hw->divider.hw);  in mpfs_ccc_register_outputs()
176 			return dev_err_probe(dev, ret, "failed to register clock id: %d\n",  in mpfs_ccc_register_outputs()
177 					     out_hw->id);  in mpfs_ccc_register_outputs()
179 		data->hw_data.hws[out_hw->id] = &out_hw->divider.hw;  in mpfs_ccc_register_outputs()
203 		pll_hw->base = data->pll_base[i];  in mpfs_ccc_register_plls()
204 		snprintf(name, 18, "ccc%s_pll%u", strchrnul(dev->of_node->full_name, '@'), i);  in mpfs_ccc_register_plls()
205 		pll_hw->name = (const char *)name;  in mpfs_ccc_register_plls()
206 		pll_hw->hw.init = CLK_HW_INIT_PARENTS_DATA_FIXED_SIZE(pll_hw->name,  in mpfs_ccc_register_plls()
207 								      pll_hw->parents,  in mpfs_ccc_register_plls()
210 		ret = devm_clk_hw_register(dev, &pll_hw->hw);  in mpfs_ccc_register_plls()
213 					     pll_hw->id);  in mpfs_ccc_register_plls()
215 		data->hw_data.hws[pll_hw->id] = &pll_hw->hw;  in mpfs_ccc_register_plls()
236 	clk_data = devm_kzalloc(&pdev->dev, struct_size(clk_data, hw_data.hws, num_clks),  in mpfs_ccc_probe()
239 		return -ENOMEM;  in mpfs_ccc_probe()
249 	clk_data->pll_base = pll_base;  in mpfs_ccc_probe()
250 	clk_data->hw_data.num = num_clks;  in mpfs_ccc_probe()
251 	clk_data->dev = &pdev->dev;  in mpfs_ccc_probe()
253 	ret = mpfs_ccc_register_plls(clk_data->dev, mpfs_ccc_pll_clks,  in mpfs_ccc_probe()
258 	return devm_of_clk_add_hw_provider(clk_data->dev, of_clk_hw_onecell_get,  in mpfs_ccc_probe()
259 					   &clk_data->hw_data);  in mpfs_ccc_probe()
263 	{ .compatible = "microchip,mpfs-ccc", },
271 		.name = "microchip-mpfs-ccc",
288 MODULE_DESCRIPTION("Microchip PolarFire SoC Clock Conditioning Circuitry Driver");