Lines Matching +full:data +full:- +full:shift
1 // SPDX-License-Identifier: GPL-2.0+
3 * Amlogic Meson-AXG Clock Controller Driver
11 #include <linux/clk-provider.h>
13 #include <linux/reset-controller.h>
16 #include "meson-aoclk.h"
17 #include "g12a-aoclk.h"
19 #include "clk-regmap.h"
20 #include "clk-dualdiv.h"
24 * Register offsets from the data sheet must be multiplied by 4.
46 .data = &(struct clk_regmap_gate_data) { \
54 .fw_name = "mpeg-clk", \
78 .data = &(struct clk_regmap_gate_data){
105 .data = &(struct clk_regmap_gate_data){
120 .data = &(struct meson_clk_dualdiv_data){
123 .shift = 0,
128 .shift = 12,
133 .shift = 0,
138 .shift = 12,
143 .shift = 28,
159 .data = &(struct clk_regmap_mux_data) {
162 .shift = 24,
178 .data = &(struct clk_regmap_gate_data){
196 .data = &(struct clk_regmap_gate_data){
211 .data = &(struct meson_clk_dualdiv_data){
214 .shift = 0,
219 .shift = 12,
224 .shift = 0,
229 .shift = 12,
234 .shift = 28,
250 .data = &(struct clk_regmap_mux_data) {
253 .shift = 24,
269 .data = &(struct clk_regmap_gate_data){
285 .data = &(struct clk_regmap_mux_data) {
288 .shift = 10,
296 { .fw_name = "ext-32k-0", },
304 .data = &(struct clk_regmap_mux_data) {
307 .shift = 8,
314 { .fw_name = "mpeg-clk", },
323 .data = &(struct clk_regmap_mux_data) {
326 .shift = 9,
340 .data = &(struct clk_regmap_div_data) {
342 .shift = 0,
357 .data = &(struct clk_regmap_gate_data) {
460 .compatible = "amlogic,meson-g12a-aoclkc",
461 .data = &g12a_aoclkc_data,
470 .name = "g12a-aoclkc",