1 // SPDX-License-Identifier: GPL-2.0
11  * In the most basic form, a Meson PLL is composed as follows:
13  *                     PLL
14  *        +--------------------------------+
16  *        |             +--+               |
17  *  in >>-----[ /N ]--->|  |      +-----+  |
18  *        |             |  |------| DCO |---->> out
19  *        |  +--------->|  |      +--v--+  |
20  *        |  |          +--+         |     |
22  *        |  +--[ *(M + (F/Fmax) ]<--+     |
24  *        +--------------------------------+
29 #include <linux/clk-provider.h>
37 #include "clk-regmap.h"
38 #include "clk-pll.h"
43 	return (struct meson_clk_pll_data *)clk->data;  in meson_clk_pll_data()
46 static int __pll_round_closest_mult(struct meson_clk_pll_data *pll)  in __pll_round_closest_mult()  argument
48 	if ((pll->flags & CLK_MESON_PLL_ROUND_CLOSEST) &&  in __pll_round_closest_mult()
49 	    !MESON_PARM_APPLICABLE(&pll->frac))  in __pll_round_closest_mult()
58 					  struct meson_clk_pll_data *pll)  in __pll_params_to_rate()  argument
62 	if (frac && MESON_PARM_APPLICABLE(&pll->frac)) {  in __pll_params_to_rate()
66 					 (1 << pll->frac.width));  in __pll_params_to_rate()
76 	struct meson_clk_pll_data *pll = meson_clk_pll_data(clk);  in meson_clk_pll_recalc_rate()  local
79 	n = meson_parm_read(clk->map, &pll->n);  in meson_clk_pll_recalc_rate()
89 	m = meson_parm_read(clk->map, &pll->m);  in meson_clk_pll_recalc_rate()
91 	frac = MESON_PARM_APPLICABLE(&pll->frac) ?  in meson_clk_pll_recalc_rate()
92 		meson_parm_read(clk->map, &pll->frac) :  in meson_clk_pll_recalc_rate()
95 	return __pll_params_to_rate(parent_rate, m, n, frac, pll);  in meson_clk_pll_recalc_rate()
102 					   struct meson_clk_pll_data *pll)  in __pll_params_with_frac()  argument
104 	unsigned int frac_max = (1 << pll->frac.width);  in __pll_params_with_frac()
111 	if (pll->flags & CLK_MESON_PLL_ROUND_CLOSEST)  in __pll_params_with_frac()
116 	val -= m * frac_max;  in __pll_params_with_frac()
118 	return min((unsigned int)val, (frac_max - 1));  in __pll_params_with_frac()
124 				    struct meson_clk_pll_data *pll)  in meson_clk_pll_is_better()  argument
126 	if (__pll_round_closest_mult(pll)) {  in meson_clk_pll_is_better()
128 		if (abs(now - rate) < abs(best - rate))  in meson_clk_pll_is_better()
142 					 struct meson_clk_pll_data *pll)  in meson_clk_get_pll_table_index()  argument
144 	if (!pll->table[index].n)  in meson_clk_get_pll_table_index()
145 		return -EINVAL;  in meson_clk_get_pll_table_index()
147 	*m = pll->table[index].m;  in meson_clk_get_pll_table_index()
148 	*n = pll->table[index].n;  in meson_clk_get_pll_table_index()
156 					      struct meson_clk_pll_data *pll)  in meson_clk_get_pll_range_m()  argument
160 	if (__pll_round_closest_mult(pll))  in meson_clk_get_pll_range_m()
171 					 struct meson_clk_pll_data *pll)  in meson_clk_get_pll_range_index()  argument
176 	if (*n >= (1 << pll->n.width))  in meson_clk_get_pll_range_index()
177 		return -EINVAL;  in meson_clk_get_pll_range_index()
181 		if (rate <= pll->range->min * parent_rate) {  in meson_clk_get_pll_range_index()
182 			*m = pll->range->min;  in meson_clk_get_pll_range_index()
183 			return -ENODATA;  in meson_clk_get_pll_range_index()
184 		} else if (rate >= pll->range->max * parent_rate) {  in meson_clk_get_pll_range_index()
185 			*m = pll->range->max;  in meson_clk_get_pll_range_index()
186 			return -ENODATA;  in meson_clk_get_pll_range_index()
190 	*m = meson_clk_get_pll_range_m(rate, parent_rate, *n, pll);  in meson_clk_get_pll_range_index()
192 	/* the pre-divider gives a multiplier too big - stop */  in meson_clk_get_pll_range_index()
193 	if (*m >= (1 << pll->m.width))  in meson_clk_get_pll_range_index()
194 		return -EINVAL;  in meson_clk_get_pll_range_index()
204 				       struct meson_clk_pll_data *pll)  in meson_clk_get_pll_get_index()  argument
206 	if (pll->range)  in meson_clk_get_pll_get_index()
208 						     index, m, n, pll);  in meson_clk_get_pll_get_index()
209 	else if (pll->table)  in meson_clk_get_pll_get_index()
210 		return meson_clk_get_pll_table_index(index, m, n, pll);  in meson_clk_get_pll_get_index()
212 	return -EINVAL;  in meson_clk_get_pll_get_index()
219 				      struct meson_clk_pll_data *pll)  in meson_clk_get_pll_settings()  argument
227 						  i, &m, &n, pll);  in meson_clk_get_pll_settings()
228 		if (ret == -EINVAL)  in meson_clk_get_pll_settings()
231 		now = __pll_params_to_rate(parent_rate, m, n, 0, pll);  in meson_clk_get_pll_settings()
232 		if (meson_clk_pll_is_better(rate, best, now, pll)) {  in meson_clk_get_pll_settings()
242 	return best ? 0 : -EINVAL;  in meson_clk_get_pll_settings()
249 	struct meson_clk_pll_data *pll = meson_clk_pll_data(clk);  in meson_clk_pll_determine_rate()  local
254 	ret = meson_clk_get_pll_settings(req->rate, req->best_parent_rate,  in meson_clk_pll_determine_rate()
255 					 &m, &n, pll);  in meson_clk_pll_determine_rate()
259 	round = __pll_params_to_rate(req->best_parent_rate, m, n, 0, pll);  in meson_clk_pll_determine_rate()
261 	if (!MESON_PARM_APPLICABLE(&pll->frac) || req->rate == round) {  in meson_clk_pll_determine_rate()
262 		req->rate = round;  in meson_clk_pll_determine_rate()
270 	frac = __pll_params_with_frac(req->rate, req->best_parent_rate, m, n, pll);  in meson_clk_pll_determine_rate()
271 	req->rate = __pll_params_to_rate(req->best_parent_rate, m, n, frac, pll);  in meson_clk_pll_determine_rate()
279 	struct meson_clk_pll_data *pll = meson_clk_pll_data(clk);  in meson_clk_pll_wait_lock()  local
284 		if (meson_parm_read(clk->map, &pll->l))  in meson_clk_pll_wait_lock()
287 		delay--;  in meson_clk_pll_wait_lock()
290 	return -ETIMEDOUT;  in meson_clk_pll_wait_lock()
296 	struct meson_clk_pll_data *pll = meson_clk_pll_data(clk);  in meson_clk_pll_init()  local
298 	if (pll->init_count) {  in meson_clk_pll_init()
299 		meson_parm_write(clk->map, &pll->rst, 1);  in meson_clk_pll_init()
300 		regmap_multi_reg_write(clk->map, pll->init_regs,  in meson_clk_pll_init()
301 				       pll->init_count);  in meson_clk_pll_init()
302 		meson_parm_write(clk->map, &pll->rst, 0);  in meson_clk_pll_init()
311 	struct meson_clk_pll_data *pll = meson_clk_pll_data(clk);  in meson_clk_pll_is_enabled()  local
313 	if (meson_parm_read(clk->map, &pll->rst) ||  in meson_clk_pll_is_enabled()
314 	    !meson_parm_read(clk->map, &pll->en) ||  in meson_clk_pll_is_enabled()
315 	    !meson_parm_read(clk->map, &pll->l))  in meson_clk_pll_is_enabled()
326 		return -EIO;  in meson_clk_pcie_pll_enable()
334 	struct meson_clk_pll_data *pll = meson_clk_pll_data(clk);  in meson_clk_pll_enable()  local
336 	/* do nothing if the PLL is already enabled */  in meson_clk_pll_enable()
340 	/* Make sure the pll is in reset */  in meson_clk_pll_enable()
341 	meson_parm_write(clk->map, &pll->rst, 1);  in meson_clk_pll_enable()
343 	/* Enable the pll */  in meson_clk_pll_enable()
344 	meson_parm_write(clk->map, &pll->en, 1);  in meson_clk_pll_enable()
346 	/* Take the pll out reset */  in meson_clk_pll_enable()
347 	meson_parm_write(clk->map, &pll->rst, 0);  in meson_clk_pll_enable()
350 		return -EIO;  in meson_clk_pll_enable()
358 	struct meson_clk_pll_data *pll = meson_clk_pll_data(clk);  in meson_clk_pll_disable()  local
360 	/* Put the pll is in reset */  in meson_clk_pll_disable()
361 	meson_parm_write(clk->map, &pll->rst, 1);  in meson_clk_pll_disable()
363 	/* Disable the pll */  in meson_clk_pll_disable()
364 	meson_parm_write(clk->map, &pll->en, 0);  in meson_clk_pll_disable()
371 	struct meson_clk_pll_data *pll = meson_clk_pll_data(clk);  in meson_clk_pll_set_rate()  local
377 		return -EINVAL;  in meson_clk_pll_set_rate()
381 	ret = meson_clk_get_pll_settings(rate, parent_rate, &m, &n, pll);  in meson_clk_pll_set_rate()
385 	enabled = meson_parm_read(clk->map, &pll->en);  in meson_clk_pll_set_rate()
389 	meson_parm_write(clk->map, &pll->n, n);  in meson_clk_pll_set_rate()
390 	meson_parm_write(clk->map, &pll->m, m);  in meson_clk_pll_set_rate()
392 	if (MESON_PARM_APPLICABLE(&pll->frac)) {  in meson_clk_pll_set_rate()
393 		frac = __pll_params_with_frac(rate, parent_rate, m, n, pll);  in meson_clk_pll_set_rate()
394 		meson_parm_write(clk->map, &pll->frac, frac);  in meson_clk_pll_set_rate()
397 	/* If the pll is stopped, bail out now */  in meson_clk_pll_set_rate()
403 		pr_warn("%s: pll did not lock, trying to restore old rate %lu\n",  in meson_clk_pll_set_rate()
418  * The Meson G12A PCIE PLL is fined tuned to deliver a very precise
420  * a strict register sequence to enable the PLL.
421  * To simplify, re-use the _init() op to enable the PLL and keep
450 MODULE_DESCRIPTION("Amlogic PLL driver");