Lines Matching +full:data +full:- +full:shift
1 // SPDX-License-Identifier: GPL-2.0+
3 * AmLogic Meson-AXG Clock Controller Driver
12 #include <linux/clk-provider.h>
18 #include "clk-regmap.h"
19 #include "clk-pll.h"
20 #include "clk-mpll.h"
22 #include "meson-eeclk.h"
27 .data = &(struct meson_clk_pll_data){
30 .shift = 30,
35 .shift = 0,
40 .shift = 9,
45 .shift = 0,
50 .shift = 31,
55 .shift = 29,
70 .data = &(struct clk_regmap_div_data){
72 .shift = 16,
91 .data = &(struct meson_clk_pll_data){
94 .shift = 30,
99 .shift = 0,
104 .shift = 9,
109 .shift = 31,
114 .shift = 29,
129 .data = &(struct clk_regmap_div_data){
131 .shift = 16,
188 .data = &(struct meson_clk_pll_data){
191 .shift = 30,
196 .shift = 0,
201 .shift = 9,
206 .shift = 0,
211 .shift = 31,
216 .shift = 29,
234 .data = &(struct clk_regmap_div_data){
236 .shift = 16,
260 .data = &(struct meson_clk_pll_data){
263 .shift = 30,
268 .shift = 0,
273 .shift = 9,
278 .shift = 0,
283 .shift = 31,
288 .shift = 29,
307 .data = &(struct clk_regmap_div_data){
309 .shift = 16,
336 .data = &(struct clk_regmap_gate_data){
363 .data = &(struct clk_regmap_gate_data){
382 * b) CCF has a clock hand-off mechanism to make the sure the
401 .data = &(struct clk_regmap_gate_data){
427 .data = &(struct clk_regmap_gate_data){
455 .data = &(struct clk_regmap_gate_data){
470 .data = &(struct clk_regmap_div_data){
472 .shift = 12,
486 .data = &(struct meson_clk_mpll_data){
489 .shift = 0,
494 .shift = 15,
499 .shift = 16,
504 .shift = 0,
521 .data = &(struct clk_regmap_gate_data){
537 .data = &(struct meson_clk_mpll_data){
540 .shift = 0,
545 .shift = 15,
550 .shift = 16,
555 .shift = 1,
572 .data = &(struct clk_regmap_gate_data){
588 .data = &(struct meson_clk_mpll_data){
591 .shift = 0,
596 .shift = 15,
601 .shift = 16,
606 .shift = 25,
611 .shift = 2,
628 .data = &(struct clk_regmap_gate_data){
644 .data = &(struct meson_clk_mpll_data){
647 .shift = 12,
652 .shift = 11,
657 .shift = 2,
662 .shift = 3,
679 .data = &(struct clk_regmap_gate_data){
713 .data = &(struct meson_clk_pll_data){
716 .shift = 30,
721 .shift = 0,
726 .shift = 9,
731 .shift = 0,
736 .shift = 31,
741 .shift = 29,
759 .data = &(struct clk_regmap_div_data){
761 .shift = 16,
777 .data = &(struct clk_regmap_div_data){
779 .shift = 6,
795 .data = &(struct clk_regmap_mux_data){
798 .shift = 2,
812 .data = &(struct clk_regmap_mux_data){
815 .shift = 1,
829 .data = &(struct clk_regmap_gate_data){
844 .data = &(struct clk_regmap_gate_data){
869 .data = &(struct clk_regmap_mux_data){
872 .shift = 12,
884 .data = &(struct clk_regmap_div_data){
886 .shift = 0,
901 .data = &(struct clk_regmap_gate_data){
932 .data = &(struct clk_regmap_mux_data){
935 .shift = 25,
947 .data = &(struct clk_regmap_div_data){
949 .shift = 16,
965 .data = &(struct clk_regmap_gate_data){
982 .data = &(struct clk_regmap_mux_data){
985 .shift = 9,
997 .data = &(struct clk_regmap_div_data){
999 .shift = 0,
1015 .data = &(struct clk_regmap_gate_data){
1040 .data = &(struct clk_regmap_mux_data){
1043 .shift = 9,
1056 .data = &(struct clk_regmap_div_data){
1058 .shift = 0,
1071 .data = &(struct clk_regmap_gate_data){
1089 .data = &(struct clk_regmap_mux_data){
1092 .shift = 25,
1105 .data = &(struct clk_regmap_div_data){
1107 .shift = 16,
1120 .data = &(struct clk_regmap_gate_data){
1138 .data = &(struct clk_regmap_mux_data){
1141 .shift = 31,
1158 .data = &(struct clk_regmap_mux_data){
1161 .shift = 9,
1173 .data = &(struct clk_regmap_div_data){
1175 .shift = 0,
1190 .data = &(struct clk_regmap_gate_data){
1206 .data = &(struct clk_regmap_mux_data){
1209 .shift = 25,
1221 .data = &(struct clk_regmap_div_data){
1223 .shift = 16,
1238 .data = &(struct clk_regmap_gate_data){
1254 .data = &(struct clk_regmap_mux_data){
1257 .shift = 31,
1272 .data = &(struct clk_regmap_gate_data){
1298 .data = &(struct clk_regmap_mux_data){
1301 .shift = 16,
1313 .data = &(struct clk_regmap_mux_data){
1316 .shift = 16,
1328 .data = &(struct clk_regmap_gate_data){
1342 .data = &(struct clk_regmap_gate_data){
1356 .data = &(struct clk_regmap_div_data){
1358 .shift = 0,
1373 .data = &(struct clk_regmap_div_data){
1375 .shift = 0,
1390 .data = &(struct clk_regmap_gate_data){
1404 .data = &(struct clk_regmap_gate_data){
1418 .data = &(struct clk_regmap_gate_data){
1432 .data = &(struct clk_regmap_gate_data){
1446 .data = &(struct clk_regmap_gate_data){
1460 .data = &(struct clk_regmap_gate_data){
1474 .data = &(struct clk_regmap_gate_data){
1488 .data = &(struct clk_regmap_gate_data){
1502 .data = &(struct clk_regmap_gate_data){
1516 .data = &(struct clk_regmap_gate_data){
1530 .data = &(struct clk_regmap_gate_data){
1544 .data = &(struct clk_regmap_gate_data){
1676 .data = &(struct clk_regmap_mux_data){
1679 .shift = 12,
1692 .data = &(struct clk_regmap_gate_data){
1720 .data = &(struct clk_regmap_mux_data){
1723 .shift = 21,
1737 .data = &(struct clk_regmap_div_data){
1739 .shift = 12,
1753 .data = &(struct clk_regmap_gate_data){
1784 .data = &(struct clk_regmap_mux_data){
1787 .shift = 12,
1805 .data = &(struct clk_regmap_div_data){
1807 .shift = 0,
1822 .data = &(struct clk_regmap_gate_data){
2171 { .compatible = "amlogic,axg-clkc", .data = &axg_clkc_data },
2179 .name = "axg-clkc",