394 		 0x0ec, 0, 2, 7),
413 #define CLK_CFG_UPDATE 0x004
414 #define CLK_CFG_UPDATE1 0x008
419 				   0x040, 0x044, 0x048, 0, 2, 7, CLK_CFG_UPDATE,
420 				   0, CLK_IS_CRITICAL),
421 	MUX_GATE_CLR_SET_UPD(CLK_TOP_MEM_SEL, "mem_sel", mem_parents, 0x040,
422 			     0x044, 0x048, 8, 2, 15, CLK_CFG_UPDATE, 1),
423 	MUX_GATE_CLR_SET_UPD(CLK_TOP_MM_SEL, "mm_sel", mm_parents, 0x040, 0x044,
424 			     0x048, 16, 3, 23, CLK_CFG_UPDATE, 2),
425 	MUX_GATE_CLR_SET_UPD(CLK_TOP_SCP_SEL, "scp_sel", scp_parents, 0x040,
426 			     0x044, 0x048, 24, 3, 31, CLK_CFG_UPDATE, 3),
428 	MUX_GATE_CLR_SET_UPD(CLK_TOP_MFG_SEL, "mfg_sel", mfg_parents, 0x050,
429 			     0x054, 0x058, 0, 2, 7, CLK_CFG_UPDATE, 4),
430 	MUX_GATE_CLR_SET_UPD(CLK_TOP_ATB_SEL, "atb_sel", atb_parents, 0x050,
431 			     0x054, 0x058, 8, 2, 15, CLK_CFG_UPDATE, 5),
433 			     0x050, 0x054, 0x058, 16, 3, 23, CLK_CFG_UPDATE, 6),
435 			     0x050, 0x054, 0x058, 24, 3, 31, CLK_CFG_UPDATE, 7),
437 	MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x060,
438 			     0x064, 0x068, 0, 1, 7, CLK_CFG_UPDATE, 8),
439 	MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x060,
440 			     0x064, 0x068, 8, 2, 15, CLK_CFG_UPDATE, 9),
442 			     msdc50_0_hc_parents, 0x060, 0x064, 0x068, 16, 2,
445 			     msdc50_0_hc_parents, 0x060, 0x064, 0x068, 24, 2,
449 			     msdc50_0_parents, 0x070, 0x074, 0x078, 0, 3, 7,
452 			     msdc50_2_parents, 0x070, 0x074, 0x078, 8, 3, 15,
455 			     msdc30_1_parents, 0x070, 0x074, 0x078, 16, 3, 23,
458 			     0x070, 0x074, 0x078, 24, 2, 31, CLK_CFG_UPDATE,
462 			     aud_intbus_parents, 0x080, 0x084, 0x088, 0, 2, 7,
465 			     0x080, 0x084, 0x088, 8, 1, 15, CLK_CFG_UPDATE, 17),
467 			     0x080, 0x084, 0x088, 16, 1, 23, CLK_CFG_UPDATE,
470 			     aud_engen1_parents, 0x080, 0x084, 0x088, 24, 2, 31,
474 			     aud_engen2_parents, 0x090, 0x094, 0x098, 0, 2, 7,
477 			     aud_spdif_parents, 0x090, 0x094, 0x098, 8, 1, 15,
480 			     disp_pwm_parents, 0x090, 0x094, 0x098, 16, 2, 23,
484 				   0x0a0, 0x0a4, 0x0a8, 0, 2, 7, CLK_CFG_UPDATE,
487 			     ssusb_sys_parents, 0x0a0, 0x0a4, 0x0a8, 8, 2, 15,
490 			     ssusb_sys_parents, 0x0a0, 0x0a4, 0x0a8, 16, 2, 23,
493 				   0x0a0, 0x0a4, 0x0a8, 24, 1, 31,
496 	MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C_SEL, "i2c_sel", i2c_parents, 0x0b0,
497 			     0x0b4, 0x0b8, 0, 3, 7, CLK_CFG_UPDATE, 28),
498 	MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x0b0,
499 			     0x0b4, 0x0b8, 8, 2, 15, CLK_CFG_UPDATE, 29),
501 			     0x0b0, 0x0b4, 0x0b8, 16, 2, 23, CLK_CFG_UPDATE,
504 			     aes_fde_parents, 0x0b0, 0x0b4, 0x0b8, 24, 3, 31,
508 			     0x0c0, 0x0c4, 0x0c8, 0, 2, 7, CLK_CFG_UPDATE1, 0),
509 	MUX_GATE_CLR_SET_UPD(CLK_TOP_DPI0_SEL, "dpi0_sel", dpi0_parents, 0x0c0,
510 			     0x0c4, 0x0c8, 8, 3, 15, CLK_CFG_UPDATE1, 1),
511 	MUX_GATE_CLR_SET_UPD(CLK_TOP_DPI1_SEL, "dpi1_sel", dpi0_parents, 0x0c0,
512 			     0x0c4, 0x0c8, 16, 3, 23, CLK_CFG_UPDATE1, 2),
513 	MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP_SEL, "dsp_sel", dsp_parents, 0x0c0,
514 			     0x0c4, 0x0c8, 24, 3, 31, CLK_CFG_UPDATE1, 3),
517 			     0x0d0, 0x0d4, 0x0d8, 0, 3, 7, CLK_CFG_UPDATE1, 4),
519 			     0x0d0, 0x0d4, 0x0d8, 8, 3, 15, CLK_CFG_UPDATE1, 5),
520 	MUX_GATE_CLR_SET_UPD(CLK_TOP_ECC_SEL, "ecc_sel", ecc_parents, 0x0d0,
521 			     0x0d4, 0x0d8, 16, 3, 23, CLK_CFG_UPDATE1, 6),
522 	MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_SEL, "eth_sel", eth_parents, 0x0d0,
523 			     0x0d4, 0x0d8, 24, 3, 31, CLK_CFG_UPDATE1, 7),
525 	MUX_GATE_CLR_SET_UPD(CLK_TOP_GCPU_SEL, "gcpu_sel", gcpu_parents, 0x0e0,
526 			     0x0e4, 0x0e8, 0, 3, 7, CLK_CFG_UPDATE1, 8),
528 			     gcpu_cpm_parents, 0x0e0, 0x0e4, 0x0e8, 8, 2, 15,
530 	MUX_GATE_CLR_SET_UPD(CLK_TOP_APU_SEL, "apu_sel", apu_parents, 0x0e0,
531 			     0x0e4, 0x0e8, 16, 3, 23, CLK_CFG_UPDATE1, 10),
533 			     0x0e0, 0x0e4, 0x0e8, 24, 3, 31, CLK_CFG_UPDATE1,
546 	MUX_GATE_FLAGS(CLK_MCU_BUS_SEL, "mcu_bus_sel", mcu_bus_parents, 0x7C0,
562 		  0x324, 0, 8, CLK_DIVIDER_ROUND_CLOSEST),
564 		  0x324, 8, 8, CLK_DIVIDER_ROUND_CLOSEST),
566 		  0x324, 16, 8, CLK_DIVIDER_ROUND_CLOSEST),
568 		  0x324, 24, 8, CLK_DIVIDER_ROUND_CLOSEST),
570 		  0x32c, 0, 8, CLK_DIVIDER_ROUND_CLOSEST),
583 	{ CLK_TOP_CONN_32K, "conn_32k", "clk32k", 0x0, 10, CLK_GATE_SET_TO_DISABLE },
584 	{ CLK_TOP_CONN_26M, "conn_26m", "clk26m", 0x0, 11, CLK_GATE_SET_TO_DISABLE },
585 	{ CLK_TOP_DSP_32K, "dsp_32k", "clk32k", 0x0, 16, CLK_GATE_SET_TO_DISABLE },
586 	{ CLK_TOP_DSP_26M, "dsp_26m", "clk26m", 0x0, 17, CLK_GATE_SET_TO_DISABLE },
587 	{ CLK_TOP_USB20_48M_EN, "usb20_48m_en", "usb20_192m_d4", 0x104, 8, 0 },
588 	{ CLK_TOP_UNIVPLL_48M_EN, "univpll_48m_en", "usb20_192m_d4", 0x104, 9, 0 },
589 	{ CLK_TOP_LVDSTX_CLKDIG_EN, "lvdstx_dig_en", "lvdstx_dig_cts", 0x104, 20, 0 },
590 	{ CLK_TOP_VPLL_DPIX_EN, "vpll_dpix_en", "vpll_dpix", 0x104, 21, 0 },
591 	{ CLK_TOP_SSUSB_TOP_CK_EN, "ssusb_top_ck_en", NULL, 0x104, 22, 0 },
592 	{ CLK_TOP_SSUSB_PHY_CK_EN, "ssusb_phy_ck_en", NULL, 0x104, 23, 0 },
593 	{ CLK_TOP_AUD_I2S0_M, "aud_i2s0_m_ck", "apll12_ck_div0", 0x320, 0, 0 },
594 	{ CLK_TOP_AUD_I2S1_M, "aud_i2s1_m_ck", "apll12_ck_div1", 0x320, 1, 0 },
595 	{ CLK_TOP_AUD_I2S2_M, "aud_i2s2_m_ck", "apll12_ck_div2", 0x320, 2, 0 },
596 	{ CLK_TOP_AUD_I2S3_M, "aud_i2s3_m_ck", "apll12_ck_div3", 0x320, 3, 0 },
597 	{ CLK_TOP_AUD_TDMOUT_M, "aud_tdmout_m_ck", "apll12_ck_div4", 0x320, 4, 0 },
598 	{ CLK_TOP_AUD_TDMOUT_B, "aud_tdmout_b_ck", "apll12_ck_div4b", 0x320, 5, 0 },
599 	{ CLK_TOP_AUD_TDMIN_M, "aud_tdmin_m_ck", "apll12_ck_div5", 0x320, 6, 0 },
600 	{ CLK_TOP_AUD_TDMIN_B, "aud_tdmin_b_ck", "apll12_ck_div5b", 0x320, 7, 0 },
601 	{ CLK_TOP_AUD_SPDIF_M, "aud_spdif_m_ck", "apll12_ck_div6", 0x320, 8, 0 },
605 	.set_ofs = 0x80,
606 	.clr_ofs = 0x84,
607 	.sta_ofs = 0x90,
611 	.set_ofs = 0x88,
612 	.clr_ofs = 0x8c,
613 	.sta_ofs = 0x94,
617 	.set_ofs = 0xa4,
618 	.clr_ofs = 0xa8,
619 	.sta_ofs = 0xac,
623 	.set_ofs = 0xc0,
624 	.clr_ofs = 0xc4,
625 	.sta_ofs = 0xc8,
629 	.set_ofs = 0xd0,
630 	.clr_ofs = 0xd4,
631 	.sta_ofs = 0xd8,
681 	GATE_IFR2(CLK_IFR_PMIC_TMR, "ifr_pmic_tmr", "clk26m", 0),
716 	GATE_IFR4(CLK_IFR_PWM_FBCLK6, "ifr_pwm_fbclk6", "pwm_sel", 0),
721 	GATE_IFR5(CLK_IFR_MSDC0_SF, "ifr_msdc0_sf", "msdc50_0_sel", 0),
742 	GATE_IFR6(CLK_IFR_NFIECC, "ifr_nfiecc", "nfiecc_sel", 0),
757 	{ CLK_PERIAXI, "periaxi", "axi_sel", 0x20c, 31, 0 },
801 	{ .div = 0, .freq = MT8365_PLL_FMAX },
810 	{ .div = 0, .freq = MT8365_PLL_FMAX },
819 	{ .div = 0, .freq = MT8365_PLL_FMAX },
828 	PLL_B(CLK_APMIXED_ARMPLL, "armpll", 0x030C, 0x0318, 0x00000001, PLL_AO,
829 	      22, 0x0310, 24, 0, 0, 0, 0x0310, 0, armpll_div_table, 0, 0),
830 	PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0228, 0x0234, 0xFF000001,
831 	    HAVE_RST_BAR, 22, 0x022C, 24, 0, 0, 0, 0x022C, 0,
832 	    CON0_MT8365_RST_BAR, 0),
833 	PLL(CLK_APMIXED_UNIVPLL, "univpll2", 0x0208, 0x0214, 0xFF000001,
834 	    HAVE_RST_BAR, 22, 0x020C, 24, 0, 0, 0, 0x020C, 0,
835 	    CON0_MT8365_RST_BAR, 0),
836 	PLL_B(CLK_APMIXED_MFGPLL, "mfgpll", 0x0218, 0x0224, 0x00000001, 0, 22,
837 	      0x021C, 24, 0, 0, 0, 0x021C, 0, mfgpll_div_table, 0, 0),
838 	PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0350, 0x035C, 0x00000001, 0, 22,
839 	    0x0354, 24, 0, 0, 0, 0x0354, 0, 0, 0),
840 	PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0330, 0x033C, 0x00000001, 0, 22,
841 	    0x0334, 24, 0, 0, 0, 0x0334, 0, 0, 0),
842 	PLL(CLK_APMIXED_APLL1, "apll1", 0x031C, 0x032C, 0x00000001, 0, 32,
843 	    0x0320, 24, 0x0040, 0x000C, 0, 0x0324, 0, 0, 0x0320),
844 	PLL(CLK_APMIXED_APLL2, "apll2", 0x0360, 0x0370, 0x00000001, 0, 32,
845 	    0x0364, 24, 0x004C, 0x000C, 5, 0x0368, 0, 0, 0x0364),
846 	PLL(CLK_APMIXED_LVDSPLL, "lvdspll", 0x0374, 0x0380, 0x00000001, 0, 22,
847 	    0x0378, 24, 0, 0, 0, 0x0378, 0, 0, 0),
848 	PLL_B(CLK_APMIXED_DSPPLL, "dsppll", 0x0390, 0x039C, 0x00000001, 0, 22,
849 	      0x0394, 24, 0, 0, 0, 0x0394, 0, dsppll_div_table, 0, 0),
850 	PLL(CLK_APMIXED_APUPLL, "apupll", 0x03A0, 0x03AC, 0x00000001, 0, 22,
851 	    0x03A4, 24, 0, 0, 0, 0x03A4, 0, 0, 0),
863 	base = devm_platform_ioremap_resource(pdev, 0);  in clk_mt8365_apmixed_probe()
871 	hw = devm_clk_hw_register_gate(dev, "univ_en", "univpll2", 0,  in clk_mt8365_apmixed_probe()
872 				       base + 0x204, 0, 0, NULL);  in clk_mt8365_apmixed_probe()
877 	hw = devm_clk_hw_register_gate(dev, "usb20_en", "univ_en", 0,  in clk_mt8365_apmixed_probe()
878 				       base + 0x204, 1, 0, NULL);  in clk_mt8365_apmixed_probe()
891 	return 0;  in clk_mt8365_apmixed_probe()
907 	for (i = 0; i != num_gates; ++i) {  in clk_mt8365_register_mtk_simple_gates()
911 		hw = devm_clk_hw_register_gate(dev, gate->name, gate->parent, 0,  in clk_mt8365_register_mtk_simple_gates()
920 	return 0;  in clk_mt8365_register_mtk_simple_gates()
932 	base = devm_platform_ioremap_resource(pdev, 0);  in clk_mt8365_top_probe()
961 	for (i = 0; i != ARRAY_SIZE(top_misc_muxes); ++i) {  in clk_mt8365_top_probe()
967 					      CLK_SET_RATE_PARENT, base + 0x320,  in clk_mt8365_top_probe()
968 					      mux->shift, 1, 0, NULL);  in clk_mt8365_top_probe()
992 	return 0;  in clk_mt8365_top_probe()
1031 	return 0;  in clk_mt8365_infra_probe()
1049 	base = devm_platform_ioremap_resource(pdev, 0);  in clk_mt8365_peri_probe()
1075 	base = devm_platform_ioremap_resource(pdev, 0);  in clk_mt8365_mcu_probe()
1092 	return 0;  in clk_mt8365_mcu_probe()