Lines Matching full:cgu
3 * Ingenic SoC CGU driver
19 * @reg: the offset of the PLL's control register within the CGU
41 * @bypass_reg: the offset of the bypass control register within the CGU
65 * @reg: offset of the mux control register within the CGU
78 * @reg: offset of the divider control register within the CGU
115 * @reg: offset of the gate control register within the CGU
141 * within the clock_info array of the CGU, or -1 in entries
184 * struct ingenic_cgu - data about the CGU
185 * @np: the device tree node that caused the CGU to be probed
186 * @base: the ioremap'ed base address of the CGU registers
189 * @lock: lock to be held whilst manipulating CGU registers
204 * @cgu: a pointer to the CGU data
205 * @idx: the index of this clock in cgu->clock_info
209 struct ingenic_cgu *cgu; member
216 * ingenic_cgu_new() - create a new CGU instance
218 * which are implemented by the CGU
220 * @np: the device tree node which causes this CGU to be probed
222 * Return: a pointer to the CGU instance if initialisation is successful,
231 * @cgu: pointer to cgu data
233 * Register the clocks described by the CGU with the common clock framework.
237 int ingenic_cgu_register_clocks(struct ingenic_cgu *cgu);