Lines Matching +full:clock +full:- +full:div
1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (c) 2013-2015 Imagination Technologies
11 #include <linux/clk-provider.h>
30 return &clk->cgu->clock_info[clk->idx]; in to_clk_info()
34 * ingenic_cgu_gate_get() - get the value of clock gate register bit
38 * Retrieves the state of the clock gate bit described by info. The
39 * caller must hold cgu->lock.
47 return !!(readl(cgu->base + info->reg) & BIT(info->bit)) in ingenic_cgu_gate_get()
48 ^ info->clear_to_gate; in ingenic_cgu_gate_get()
52 * ingenic_cgu_gate_set() - set the value of clock gate register bit
55 * @val: non-zero to gate a clock, otherwise zero
57 * Sets the given gate bit in order to gate or ungate a clock.
59 * The caller must hold cgu->lock.
65 u32 clkgr = readl(cgu->base + info->reg); in ingenic_cgu_gate_set()
67 if (val ^ info->clear_to_gate) in ingenic_cgu_gate_set()
68 clkgr |= BIT(info->bit); in ingenic_cgu_gate_set()
70 clkgr &= ~BIT(info->bit); in ingenic_cgu_gate_set()
72 writel(clkgr, cgu->base + info->reg); in ingenic_cgu_gate_set()
84 struct ingenic_cgu *cgu = ingenic_clk->cgu; in ingenic_pll_recalc_rate()
90 BUG_ON(clk_info->type != CGU_CLK_PLL); in ingenic_pll_recalc_rate()
91 pll_info = &clk_info->pll; in ingenic_pll_recalc_rate()
93 ctl = readl(cgu->base + pll_info->reg); in ingenic_pll_recalc_rate()
95 m = (ctl >> pll_info->m_shift) & GENMASK(pll_info->m_bits - 1, 0); in ingenic_pll_recalc_rate()
96 m += pll_info->m_offset; in ingenic_pll_recalc_rate()
97 n = (ctl >> pll_info->n_shift) & GENMASK(pll_info->n_bits - 1, 0); in ingenic_pll_recalc_rate()
98 n += pll_info->n_offset; in ingenic_pll_recalc_rate()
99 od_enc = ctl >> pll_info->od_shift; in ingenic_pll_recalc_rate()
100 od_enc &= GENMASK(pll_info->od_bits - 1, 0); in ingenic_pll_recalc_rate()
102 if (pll_info->bypass_bit >= 0) { in ingenic_pll_recalc_rate()
103 ctl = readl(cgu->base + pll_info->bypass_reg); in ingenic_pll_recalc_rate()
105 bypass = !!(ctl & BIT(pll_info->bypass_bit)); in ingenic_pll_recalc_rate()
111 for (od = 0; od < pll_info->od_max; od++) { in ingenic_pll_recalc_rate()
112 if (pll_info->od_encoding[od] == od_enc) in ingenic_pll_recalc_rate()
115 BUG_ON(od == pll_info->od_max); in ingenic_pll_recalc_rate()
118 return div_u64((u64)parent_rate * m * pll_info->rate_multiplier, in ingenic_pll_recalc_rate()
134 n = min_t(unsigned int, n, 1 << pll_info->n_bits); in ingenic_pll_calc_m_n_od()
135 n = max_t(unsigned int, n, pll_info->n_offset); in ingenic_pll_calc_m_n_od()
138 m = min_t(unsigned int, m, 1 << pll_info->m_bits); in ingenic_pll_calc_m_n_od()
139 m = max_t(unsigned int, m, pll_info->m_offset); in ingenic_pll_calc_m_n_od()
151 const struct ingenic_cgu_pll_info *pll_info = &clk_info->pll; in ingenic_pll_calc()
154 if (pll_info->calc_m_n_od) in ingenic_pll_calc()
155 (*pll_info->calc_m_n_od)(pll_info, rate, parent_rate, &m, &n, &od); in ingenic_pll_calc()
166 return div_u64((u64)parent_rate * m * pll_info->rate_multiplier, in ingenic_pll_calc()
185 return readl_poll_timeout(cgu->base + pll_info->reg, ctl, in ingenic_pll_check_stable()
186 ctl & BIT(pll_info->stable_bit), in ingenic_pll_check_stable()
195 struct ingenic_cgu *cgu = ingenic_clk->cgu; in ingenic_pll_set_rate()
197 const struct ingenic_cgu_pll_info *pll_info = &clk_info->pll; in ingenic_pll_set_rate()
206 pr_info("ingenic-cgu: request '%s' rate %luHz, actual %luHz\n", in ingenic_pll_set_rate()
207 clk_info->name, req_rate, rate); in ingenic_pll_set_rate()
209 spin_lock_irqsave(&cgu->lock, flags); in ingenic_pll_set_rate()
210 ctl = readl(cgu->base + pll_info->reg); in ingenic_pll_set_rate()
212 ctl &= ~(GENMASK(pll_info->m_bits - 1, 0) << pll_info->m_shift); in ingenic_pll_set_rate()
213 ctl |= (m - pll_info->m_offset) << pll_info->m_shift; in ingenic_pll_set_rate()
215 ctl &= ~(GENMASK(pll_info->n_bits - 1, 0) << pll_info->n_shift); in ingenic_pll_set_rate()
216 ctl |= (n - pll_info->n_offset) << pll_info->n_shift; in ingenic_pll_set_rate()
218 ctl &= ~(GENMASK(pll_info->od_bits - 1, 0) << pll_info->od_shift); in ingenic_pll_set_rate()
219 ctl |= pll_info->od_encoding[od - 1] << pll_info->od_shift; in ingenic_pll_set_rate()
221 writel(ctl, cgu->base + pll_info->reg); in ingenic_pll_set_rate()
224 if (ctl & BIT(pll_info->enable_bit)) in ingenic_pll_set_rate()
227 spin_unlock_irqrestore(&cgu->lock, flags); in ingenic_pll_set_rate()
235 struct ingenic_cgu *cgu = ingenic_clk->cgu; in ingenic_pll_enable()
237 const struct ingenic_cgu_pll_info *pll_info = &clk_info->pll; in ingenic_pll_enable()
242 spin_lock_irqsave(&cgu->lock, flags); in ingenic_pll_enable()
243 if (pll_info->bypass_bit >= 0) { in ingenic_pll_enable()
244 ctl = readl(cgu->base + pll_info->bypass_reg); in ingenic_pll_enable()
246 ctl &= ~BIT(pll_info->bypass_bit); in ingenic_pll_enable()
248 writel(ctl, cgu->base + pll_info->bypass_reg); in ingenic_pll_enable()
251 ctl = readl(cgu->base + pll_info->reg); in ingenic_pll_enable()
253 ctl |= BIT(pll_info->enable_bit); in ingenic_pll_enable()
255 writel(ctl, cgu->base + pll_info->reg); in ingenic_pll_enable()
258 spin_unlock_irqrestore(&cgu->lock, flags); in ingenic_pll_enable()
266 struct ingenic_cgu *cgu = ingenic_clk->cgu; in ingenic_pll_disable()
268 const struct ingenic_cgu_pll_info *pll_info = &clk_info->pll; in ingenic_pll_disable()
272 spin_lock_irqsave(&cgu->lock, flags); in ingenic_pll_disable()
273 ctl = readl(cgu->base + pll_info->reg); in ingenic_pll_disable()
275 ctl &= ~BIT(pll_info->enable_bit); in ingenic_pll_disable()
277 writel(ctl, cgu->base + pll_info->reg); in ingenic_pll_disable()
278 spin_unlock_irqrestore(&cgu->lock, flags); in ingenic_pll_disable()
284 struct ingenic_cgu *cgu = ingenic_clk->cgu; in ingenic_pll_is_enabled()
286 const struct ingenic_cgu_pll_info *pll_info = &clk_info->pll; in ingenic_pll_is_enabled()
289 ctl = readl(cgu->base + pll_info->reg); in ingenic_pll_is_enabled()
291 return !!(ctl & BIT(pll_info->enable_bit)); in ingenic_pll_is_enabled()
305 * Operations for all non-PLL clocks
312 struct ingenic_cgu *cgu = ingenic_clk->cgu; in ingenic_clk_get_parent()
316 if (clk_info->type & CGU_CLK_MUX) { in ingenic_clk_get_parent()
317 reg = readl(cgu->base + clk_info->mux.reg); in ingenic_clk_get_parent()
318 hw_idx = (reg >> clk_info->mux.shift) & in ingenic_clk_get_parent()
319 GENMASK(clk_info->mux.bits - 1, 0); in ingenic_clk_get_parent()
323 * over any -1's in the parents array. in ingenic_clk_get_parent()
326 if (clk_info->parents[i] != -1) in ingenic_clk_get_parent()
338 struct ingenic_cgu *cgu = ingenic_clk->cgu; in ingenic_clk_set_parent()
343 if (clk_info->type & CGU_CLK_MUX) { in ingenic_clk_set_parent()
346 * 1 for any -1 in the parents array preceding the given in ingenic_clk_set_parent()
348 * clk_info->parents which does not equal -1. in ingenic_clk_set_parent()
351 num_poss = 1 << clk_info->mux.bits; in ingenic_clk_set_parent()
353 if (clk_info->parents[hw_idx] == -1) in ingenic_clk_set_parent()
363 mask = GENMASK(clk_info->mux.bits - 1, 0); in ingenic_clk_set_parent()
364 mask <<= clk_info->mux.shift; in ingenic_clk_set_parent()
366 spin_lock_irqsave(&cgu->lock, flags); in ingenic_clk_set_parent()
369 reg = readl(cgu->base + clk_info->mux.reg); in ingenic_clk_set_parent()
371 reg |= hw_idx << clk_info->mux.shift; in ingenic_clk_set_parent()
372 writel(reg, cgu->base + clk_info->mux.reg); in ingenic_clk_set_parent()
374 spin_unlock_irqrestore(&cgu->lock, flags); in ingenic_clk_set_parent()
378 return idx ? -EINVAL : 0; in ingenic_clk_set_parent()
386 struct ingenic_cgu *cgu = ingenic_clk->cgu; in ingenic_clk_recalc_rate()
388 u32 div_reg, div; in ingenic_clk_recalc_rate() local
391 if (clk_info->type & CGU_CLK_DIV) { in ingenic_clk_recalc_rate()
394 if (!(clk_info->div.bypass_mask & BIT(parent))) { in ingenic_clk_recalc_rate()
395 div_reg = readl(cgu->base + clk_info->div.reg); in ingenic_clk_recalc_rate()
396 div = (div_reg >> clk_info->div.shift) & in ingenic_clk_recalc_rate()
397 GENMASK(clk_info->div.bits - 1, 0); in ingenic_clk_recalc_rate()
399 if (clk_info->div.div_table) in ingenic_clk_recalc_rate()
400 div = clk_info->div.div_table[div]; in ingenic_clk_recalc_rate()
402 div = (div + 1) * clk_info->div.div; in ingenic_clk_recalc_rate()
404 rate /= div; in ingenic_clk_recalc_rate()
406 } else if (clk_info->type & CGU_CLK_FIXDIV) { in ingenic_clk_recalc_rate()
407 rate /= clk_info->fixdiv.div; in ingenic_clk_recalc_rate()
415 unsigned int div) in ingenic_clk_calc_hw_div() argument
417 unsigned int i, best_i = 0, best = (unsigned int)-1; in ingenic_clk_calc_hw_div()
419 for (i = 0; i < (1 << clk_info->div.bits) in ingenic_clk_calc_hw_div()
420 && clk_info->div.div_table[i]; i++) { in ingenic_clk_calc_hw_div()
421 if (clk_info->div.div_table[i] >= div && in ingenic_clk_calc_hw_div()
422 clk_info->div.div_table[i] < best) { in ingenic_clk_calc_hw_div()
423 best = clk_info->div.div_table[i]; in ingenic_clk_calc_hw_div()
426 if (div == best) in ingenic_clk_calc_hw_div()
439 unsigned int div, hw_div; in ingenic_clk_calc_div() local
443 if (clk_info->div.bypass_mask & BIT(parent)) in ingenic_clk_calc_div()
447 div = DIV_ROUND_UP(parent_rate, req_rate); in ingenic_clk_calc_div()
449 if (clk_info->div.div_table) { in ingenic_clk_calc_div()
450 hw_div = ingenic_clk_calc_hw_div(clk_info, div); in ingenic_clk_calc_div()
452 return clk_info->div.div_table[hw_div]; in ingenic_clk_calc_div()
456 div = clamp_t(unsigned int, div, clk_info->div.div, in ingenic_clk_calc_div()
457 clk_info->div.div << clk_info->div.bits); in ingenic_clk_calc_div()
464 div = DIV_ROUND_UP(div, clk_info->div.div); in ingenic_clk_calc_div()
465 div *= clk_info->div.div; in ingenic_clk_calc_div()
467 return div; in ingenic_clk_calc_div()
476 unsigned int div = 1; in ingenic_clk_round_rate() local
478 if (clk_info->type & CGU_CLK_DIV) in ingenic_clk_round_rate()
479 div = ingenic_clk_calc_div(hw, clk_info, *parent_rate, req_rate); in ingenic_clk_round_rate()
480 else if (clk_info->type & CGU_CLK_FIXDIV) in ingenic_clk_round_rate()
481 div = clk_info->fixdiv.div; in ingenic_clk_round_rate()
485 return DIV_ROUND_UP(*parent_rate, div); in ingenic_clk_round_rate()
493 return readl_poll_timeout(cgu->base + clk_info->div.reg, reg, in ingenic_clk_check_stable()
494 !(reg & BIT(clk_info->div.busy_bit)), in ingenic_clk_check_stable()
504 struct ingenic_cgu *cgu = ingenic_clk->cgu; in ingenic_clk_set_rate()
506 unsigned int hw_div, div; in ingenic_clk_set_rate() local
510 if (clk_info->type & CGU_CLK_DIV) { in ingenic_clk_set_rate()
511 div = ingenic_clk_calc_div(hw, clk_info, parent_rate, req_rate); in ingenic_clk_set_rate()
512 rate = DIV_ROUND_UP(parent_rate, div); in ingenic_clk_set_rate()
515 return -EINVAL; in ingenic_clk_set_rate()
517 if (clk_info->div.div_table) in ingenic_clk_set_rate()
518 hw_div = ingenic_clk_calc_hw_div(clk_info, div); in ingenic_clk_set_rate()
520 hw_div = ((div / clk_info->div.div) - 1); in ingenic_clk_set_rate()
522 spin_lock_irqsave(&cgu->lock, flags); in ingenic_clk_set_rate()
523 reg = readl(cgu->base + clk_info->div.reg); in ingenic_clk_set_rate()
526 mask = GENMASK(clk_info->div.bits - 1, 0); in ingenic_clk_set_rate()
527 reg &= ~(mask << clk_info->div.shift); in ingenic_clk_set_rate()
528 reg |= hw_div << clk_info->div.shift; in ingenic_clk_set_rate()
531 if (clk_info->div.stop_bit != -1) in ingenic_clk_set_rate()
532 reg &= ~BIT(clk_info->div.stop_bit); in ingenic_clk_set_rate()
535 if (clk_info->div.ce_bit != -1) in ingenic_clk_set_rate()
536 reg |= BIT(clk_info->div.ce_bit); in ingenic_clk_set_rate()
539 writel(reg, cgu->base + clk_info->div.reg); in ingenic_clk_set_rate()
542 if (clk_info->div.busy_bit != -1) in ingenic_clk_set_rate()
545 spin_unlock_irqrestore(&cgu->lock, flags); in ingenic_clk_set_rate()
549 return -EINVAL; in ingenic_clk_set_rate()
556 struct ingenic_cgu *cgu = ingenic_clk->cgu; in ingenic_clk_enable()
559 if (clk_info->type & CGU_CLK_GATE) { in ingenic_clk_enable()
560 /* ungate the clock */ in ingenic_clk_enable()
561 spin_lock_irqsave(&cgu->lock, flags); in ingenic_clk_enable()
562 ingenic_cgu_gate_set(cgu, &clk_info->gate, false); in ingenic_clk_enable()
563 spin_unlock_irqrestore(&cgu->lock, flags); in ingenic_clk_enable()
565 if (clk_info->gate.delay_us) in ingenic_clk_enable()
566 udelay(clk_info->gate.delay_us); in ingenic_clk_enable()
576 struct ingenic_cgu *cgu = ingenic_clk->cgu; in ingenic_clk_disable()
579 if (clk_info->type & CGU_CLK_GATE) { in ingenic_clk_disable()
580 /* gate the clock */ in ingenic_clk_disable()
581 spin_lock_irqsave(&cgu->lock, flags); in ingenic_clk_disable()
582 ingenic_cgu_gate_set(cgu, &clk_info->gate, true); in ingenic_clk_disable()
583 spin_unlock_irqrestore(&cgu->lock, flags); in ingenic_clk_disable()
591 struct ingenic_cgu *cgu = ingenic_clk->cgu; in ingenic_clk_is_enabled()
594 if (clk_info->type & CGU_CLK_GATE) in ingenic_clk_is_enabled()
595 enabled = !ingenic_cgu_gate_get(cgu, &clk_info->gate); in ingenic_clk_is_enabled()
619 const struct ingenic_cgu_clk_info *clk_info = &cgu->clock_info[idx]; in ingenic_register_clock()
625 int err = -EINVAL; in ingenic_register_clock()
627 BUILD_BUG_ON(ARRAY_SIZE(clk_info->parents) > ARRAY_SIZE(parent_names)); in ingenic_register_clock()
629 if (clk_info->type == CGU_CLK_EXT) { in ingenic_register_clock()
630 clk = of_clk_get_by_name(cgu->np, clk_info->name); in ingenic_register_clock()
632 pr_err("%s: no external clock '%s' provided\n", in ingenic_register_clock()
633 __func__, clk_info->name); in ingenic_register_clock()
634 err = -ENODEV; in ingenic_register_clock()
637 err = clk_register_clkdev(clk, clk_info->name, NULL); in ingenic_register_clock()
642 cgu->clocks.clks[idx] = clk; in ingenic_register_clock()
646 if (!clk_info->type) { in ingenic_register_clock()
647 pr_err("%s: no clock type specified for '%s'\n", __func__, in ingenic_register_clock()
648 clk_info->name); in ingenic_register_clock()
654 err = -ENOMEM; in ingenic_register_clock()
658 ingenic_clk->hw.init = &clk_init; in ingenic_register_clock()
659 ingenic_clk->cgu = cgu; in ingenic_register_clock()
660 ingenic_clk->idx = idx; in ingenic_register_clock()
662 clk_init.name = clk_info->name; in ingenic_register_clock()
663 clk_init.flags = clk_info->flags; in ingenic_register_clock()
666 caps = clk_info->type; in ingenic_register_clock()
671 /* pass rate changes to the parent clock */ in ingenic_register_clock()
679 num_possible = 1 << clk_info->mux.bits; in ingenic_register_clock()
681 num_possible = ARRAY_SIZE(clk_info->parents); in ingenic_register_clock()
684 if (clk_info->parents[i] == -1) in ingenic_register_clock()
687 parent = cgu->clocks.clks[clk_info->parents[i]]; in ingenic_register_clock()
696 BUG_ON(clk_info->parents[0] == -1); in ingenic_register_clock()
698 parent = cgu->clocks.clks[clk_info->parents[0]]; in ingenic_register_clock()
703 clk_init.ops = clk_info->custom.clk_ops; in ingenic_register_clock()
708 pr_err("%s: custom clock may not be combined with type 0x%x\n", in ingenic_register_clock()
737 pr_err("%s: unknown clock type 0x%x\n", __func__, caps); in ingenic_register_clock()
741 clk = clk_register(NULL, &ingenic_clk->hw); in ingenic_register_clock()
743 pr_err("%s: failed to register clock '%s'\n", __func__, in ingenic_register_clock()
744 clk_info->name); in ingenic_register_clock()
749 err = clk_register_clkdev(clk, clk_info->name, NULL); in ingenic_register_clock()
753 cgu->clocks.clks[idx] = clk; in ingenic_register_clock()
770 cgu->base = of_iomap(np, 0); in ingenic_cgu_new()
771 if (!cgu->base) { in ingenic_cgu_new()
776 cgu->np = np; in ingenic_cgu_new()
777 cgu->clock_info = clock_info; in ingenic_cgu_new()
778 cgu->clocks.clk_num = num_clocks; in ingenic_cgu_new()
780 spin_lock_init(&cgu->lock); in ingenic_cgu_new()
795 cgu->clocks.clks = kcalloc(cgu->clocks.clk_num, sizeof(struct clk *), in ingenic_cgu_register_clocks()
797 if (!cgu->clocks.clks) { in ingenic_cgu_register_clocks()
798 err = -ENOMEM; in ingenic_cgu_register_clocks()
802 for (i = 0; i < cgu->clocks.clk_num; i++) { in ingenic_cgu_register_clocks()
808 err = of_clk_add_provider(cgu->np, of_clk_src_onecell_get, in ingenic_cgu_register_clocks()
809 &cgu->clocks); in ingenic_cgu_register_clocks()
816 for (i = 0; i < cgu->clocks.clk_num; i++) { in ingenic_cgu_register_clocks()
817 if (!cgu->clocks.clks[i]) in ingenic_cgu_register_clocks()
819 if (cgu->clock_info[i].type & CGU_CLK_EXT) in ingenic_cgu_register_clocks()
820 clk_put(cgu->clocks.clks[i]); in ingenic_cgu_register_clocks()
822 clk_unregister(cgu->clocks.clks[i]); in ingenic_cgu_register_clocks()
824 kfree(cgu->clocks.clks); in ingenic_cgu_register_clocks()