64 				   "dummy", "lcdif_pix", "ahb", "ipg", "ipg_per", "ckil", "pll4_audio_div", };
291 	hws[IMX6UL_CLK_IPG]		= imx_clk_hw_divider("ipg",	   "ahb",		base + 0x14, 8,	 2);  in imx6ul_clocks_init()
330 …hws[IMX6UL_CLK_AHB]		= imx_clk_hw_busy_divider("ahb",	    "periph",	base +  0x14, 10, 3,  base + 0…  in imx6ul_clocks_init()
333 …hws[IMX6UL_CLK_AIPSTZ1]	= imx_clk_hw_gate2_flags("aips_tz1", "ahb", base + 0x68, 0, CLK_IS_CRITICA…  in imx6ul_clocks_init()
334 …hws[IMX6UL_CLK_AIPSTZ2]	= imx_clk_hw_gate2_flags("aips_tz2", "ahb", base + 0x68, 2, CLK_IS_CRITICA…  in imx6ul_clocks_init()
336 …hws[IMX6UL_CLK_ASRC_IPG]	= imx_clk_hw_gate2_shared("asrc_ipg",	"ahb",	base + 0x68,	6, &share_count…  in imx6ul_clocks_init()
337 …hws[IMX6UL_CLK_ASRC_MEM]	= imx_clk_hw_gate2_shared("asrc_mem",	"ahb",	base + 0x68,	6, &share_count…  in imx6ul_clocks_init()
339 		hws[IMX6UL_CLK_CAAM_MEM]	= imx_clk_hw_gate2("caam_mem",	"ahb",		base + 0x68,	8);  in imx6ul_clocks_init()
340 		hws[IMX6UL_CLK_CAAM_ACLK]	= imx_clk_hw_gate2("caam_aclk",	"ahb",		base + 0x68,	10);  in imx6ul_clocks_init()
343 		hws[IMX6ULL_CLK_DCP_CLK]	= imx_clk_hw_gate2("dcp",		"ahb",		base + 0x68,	10);  in imx6ul_clocks_init()
345 		hws[IMX6UL_CLK_ENET_AHB]	= imx_clk_hw_gate2("enet_ahb",	"ahb",		base + 0x68,	12);  in imx6ul_clocks_init()
356 		hws[IMX6UL_CLK_AIPSTZ3]	= imx_clk_hw_gate2("aips_tz3",	"ahb",		 base + 0x80,	18);  in imx6ul_clocks_init()
380 …hws[IMX6ULL_CLK_ESAI_IPG]	= imx_clk_hw_gate2_shared("esai_ipg",	"ahb",		base + 0x70,	0, &share_cou…  in imx6ul_clocks_init()
381 …hws[IMX6ULL_CLK_ESAI_MEM]	= imx_clk_hw_gate2_shared("esai_mem",	"ahb",		base + 0x70,	0, &share_cou…  in imx6ul_clocks_init()
403 		hws[IMX6UL_CLK_ENET_AHB]	= imx_clk_hw_gate2("enet_ahb",	"ahb",		base + 0x74,	4);  in imx6ul_clocks_init()
431 	hws[IMX6UL_CLK_ROM]		= imx_clk_hw_gate2_flags("rom",	"ahb",		base + 0x7c,	0,	CLK_IS_CRITICAL);  in imx6ul_clocks_init()
432 	hws[IMX6UL_CLK_SDMA]		= imx_clk_hw_gate2("sdma",		"ahb",		base + 0x7c,	6);  in imx6ul_clocks_init()
479 	 * Lower the AHB clock rate before changing the parent clock source,  in imx6ul_clocks_init()
480 	 * as AHB clock rate can NOT be higher than 133MHz, but its parent  in imx6ul_clocks_init()
482 	 * AXI clock rate, so we need to lower AHB rate first to make sure at  in imx6ul_clocks_init()
483 	 * any time, AHB rate is <= 133MHz.  in imx6ul_clocks_init()
493 	/* Make sure AHB rate is 132MHz  */  in imx6ul_clocks_init()