Lines Matching +full:reg +full:- +full:mux
1 // SPDX-License-Identifier: GPL-2.0
6 #include <linux/clk-provider.h>
36 prediv_value = readl(divider->reg) >> divider->shift; in imx8m_clk_composite_divider_recalc_rate()
37 prediv_value &= clk_div_mask(divider->width); in imx8m_clk_composite_divider_recalc_rate()
40 NULL, divider->flags, in imx8m_clk_composite_divider_recalc_rate()
41 divider->width); in imx8m_clk_composite_divider_recalc_rate()
43 div_value = readl(divider->reg) >> PCG_DIV_SHIFT; in imx8m_clk_composite_divider_recalc_rate()
47 divider->flags, PCG_DIV_WIDTH); in imx8m_clk_composite_divider_recalc_rate()
56 int ret = -EINVAL; in imx8m_clk_composite_compute_dividers()
63 int new_error = ((parent_rate / div1) / div2) - rate; in imx8m_clk_composite_compute_dividers()
105 return -EINVAL; in imx8m_clk_composite_divider_set_rate()
107 spin_lock_irqsave(divider->lock, flags); in imx8m_clk_composite_divider_set_rate()
109 val = readl(divider->reg); in imx8m_clk_composite_divider_set_rate()
110 val &= ~((clk_div_mask(divider->width) << divider->shift) | in imx8m_clk_composite_divider_set_rate()
113 val |= (u32)(prediv_value - 1) << divider->shift; in imx8m_clk_composite_divider_set_rate()
114 val |= (u32)(div_value - 1) << PCG_DIV_SHIFT; in imx8m_clk_composite_divider_set_rate()
115 writel(val, divider->reg); in imx8m_clk_composite_divider_set_rate()
117 spin_unlock_irqrestore(divider->lock, flags); in imx8m_clk_composite_divider_set_rate()
135 struct clk_mux *mux = to_clk_mux(hw); in imx8m_clk_composite_mux_set_parent() local
136 u32 val = clk_mux_index_to_val(mux->table, mux->flags, index); in imx8m_clk_composite_mux_set_parent()
138 u32 reg; in imx8m_clk_composite_mux_set_parent() local
140 if (mux->lock) in imx8m_clk_composite_mux_set_parent()
141 spin_lock_irqsave(mux->lock, flags); in imx8m_clk_composite_mux_set_parent()
143 reg = readl(mux->reg); in imx8m_clk_composite_mux_set_parent()
144 reg &= ~(mux->mask << mux->shift); in imx8m_clk_composite_mux_set_parent()
145 val = val << mux->shift; in imx8m_clk_composite_mux_set_parent()
146 reg |= val; in imx8m_clk_composite_mux_set_parent()
148 * write twice to make sure non-target interface in imx8m_clk_composite_mux_set_parent()
151 writel(reg, mux->reg); in imx8m_clk_composite_mux_set_parent()
152 writel(reg, mux->reg); in imx8m_clk_composite_mux_set_parent()
154 if (mux->lock) in imx8m_clk_composite_mux_set_parent()
155 spin_unlock_irqrestore(mux->lock, flags); in imx8m_clk_composite_mux_set_parent()
176 int num_parents, void __iomem *reg, in __imx8m_clk_hw_composite() argument
180 struct clk_hw *hw = ERR_PTR(-ENOMEM), *mux_hw; in __imx8m_clk_hw_composite()
184 struct clk_mux *mux = NULL; in __imx8m_clk_hw_composite() local
188 mux = kzalloc(sizeof(*mux), GFP_KERNEL); in __imx8m_clk_hw_composite()
189 if (!mux) in __imx8m_clk_hw_composite()
192 mux_hw = &mux->hw; in __imx8m_clk_hw_composite()
193 mux->reg = reg; in __imx8m_clk_hw_composite()
194 mux->shift = PCG_PCS_SHIFT; in __imx8m_clk_hw_composite()
195 mux->mask = PCG_PCS_MASK; in __imx8m_clk_hw_composite()
196 mux->lock = &imx_ccm_lock; in __imx8m_clk_hw_composite()
202 div_hw = &div->hw; in __imx8m_clk_hw_composite()
203 div->reg = reg; in __imx8m_clk_hw_composite()
205 div->shift = PCG_DIV_SHIFT; in __imx8m_clk_hw_composite()
206 div->width = PCG_CORE_DIV_WIDTH; in __imx8m_clk_hw_composite()
210 div->shift = PCG_PREDIV_SHIFT; in __imx8m_clk_hw_composite()
211 div->width = PCG_PREDIV_WIDTH; in __imx8m_clk_hw_composite()
215 div->shift = PCG_PREDIV_SHIFT; in __imx8m_clk_hw_composite()
216 div->width = PCG_PREDIV_WIDTH; in __imx8m_clk_hw_composite()
223 div->lock = &imx_ccm_lock; in __imx8m_clk_hw_composite()
224 div->flags = CLK_DIVIDER_ROUND_CLOSEST; in __imx8m_clk_hw_composite()
232 gate_hw = &gate->hw; in __imx8m_clk_hw_composite()
233 gate->reg = reg; in __imx8m_clk_hw_composite()
234 gate->bit_idx = PCG_CGC_SHIFT; in __imx8m_clk_hw_composite()
235 gate->lock = &imx_ccm_lock; in __imx8m_clk_hw_composite()
249 kfree(mux); in __imx8m_clk_hw_composite()