Lines Matching +full:mux +full:- +full:locked
1 // SPDX-License-Identifier: GPL-2.0
3 * Clock driver for DA8xx/AM17xx/AM18xx/OMAP-L13x CFGCHIP
8 #include <linux/clk-provider.h>
12 #include <linux/mfd/da8xx-cfgchip.h>
16 #include <linux/platform_data/clk-da8xx-cfgchip.h>
21 /* --- Gate clocks --- */
46 return regmap_write_bits(clk->regmap, clk->reg, clk->mask, clk->mask); in da8xx_cfgchip_gate_clk_enable()
53 regmap_write_bits(clk->regmap, clk->reg, clk->mask, 0); in da8xx_cfgchip_gate_clk_disable()
61 regmap_read(clk->regmap, clk->reg, &val); in da8xx_cfgchip_gate_clk_is_enabled()
63 return !!(val & clk->mask); in da8xx_cfgchip_gate_clk_is_enabled()
105 return ERR_PTR(-ENOMEM); in da8xx_cfgchip_gate_clk_register()
107 init.name = info->name; in da8xx_cfgchip_gate_clk_register()
108 if (info->flags & DA8XX_GATE_CLOCK_IS_DIV4P5) in da8xx_cfgchip_gate_clk_register()
116 gate->hw.init = &init; in da8xx_cfgchip_gate_clk_register()
117 gate->regmap = regmap; in da8xx_cfgchip_gate_clk_register()
118 gate->reg = info->cfgchip; in da8xx_cfgchip_gate_clk_register()
119 gate->mask = info->bit; in da8xx_cfgchip_gate_clk_register()
121 ret = devm_clk_hw_register(dev, &gate->hw); in da8xx_cfgchip_gate_clk_register()
144 clk_hw_register_clkdev(&gate->hw, "tbclk", "ehrpwm.0"); in da8xx_cfgchip_register_tbclk()
145 clk_hw_register_clkdev(&gate->hw, "tbclk", "ehrpwm.1"); in da8xx_cfgchip_register_tbclk()
193 /* --- MUX clocks --- */
216 unsigned int val = index ? clk->mask : 0; in da8xx_cfgchip_mux_clk_set_parent()
218 return regmap_write_bits(clk->regmap, clk->reg, clk->mask, val); in da8xx_cfgchip_mux_clk_set_parent()
226 regmap_read(clk->regmap, clk->reg, &val); in da8xx_cfgchip_mux_clk_get_parent()
228 return (val & clk->mask) ? 1 : 0; in da8xx_cfgchip_mux_clk_get_parent()
241 const char * const parent_names[] = { info->parent0, info->parent1 }; in da8xx_cfgchip_mux_clk_register()
242 struct da8xx_cfgchip_mux_clk *mux; in da8xx_cfgchip_mux_clk_register() local
246 mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL); in da8xx_cfgchip_mux_clk_register()
247 if (!mux) in da8xx_cfgchip_mux_clk_register()
248 return ERR_PTR(-ENOMEM); in da8xx_cfgchip_mux_clk_register()
250 init.name = info->name; in da8xx_cfgchip_mux_clk_register()
256 mux->hw.init = &init; in da8xx_cfgchip_mux_clk_register()
257 mux->regmap = regmap; in da8xx_cfgchip_mux_clk_register()
258 mux->reg = info->cfgchip; in da8xx_cfgchip_mux_clk_register()
259 mux->mask = info->bit; in da8xx_cfgchip_mux_clk_register()
261 ret = devm_clk_hw_register(dev, &mux->hw); in da8xx_cfgchip_mux_clk_register()
265 return mux; in da8xx_cfgchip_mux_clk_register()
279 struct da8xx_cfgchip_mux_clk *mux; in da8xx_cfgchip_register_async1() local
281 mux = da8xx_cfgchip_mux_clk_register(dev, &da850_async1_info, regmap); in da8xx_cfgchip_register_async1()
282 if (IS_ERR(mux)) in da8xx_cfgchip_register_async1()
283 return PTR_ERR(mux); in da8xx_cfgchip_register_async1()
285 clk_hw_register_clkdev(&mux->hw, "async1", "da850-psc0"); in da8xx_cfgchip_register_async1()
301 struct da8xx_cfgchip_mux_clk *mux; in da850_cfgchip_register_async3() local
304 mux = da8xx_cfgchip_mux_clk_register(dev, &da850_async3_info, regmap); in da850_cfgchip_register_async3()
305 if (IS_ERR(mux)) in da850_cfgchip_register_async3()
306 return PTR_ERR(mux); in da850_cfgchip_register_async3()
308 clk_hw_register_clkdev(&mux->hw, "async3", "da850-psc1"); in da850_cfgchip_register_async3()
311 parent = clk_hw_get_parent_by_index(&mux->hw, 1); in da850_cfgchip_register_async3()
313 clk_set_parent(mux->hw.clk, parent->clk); in da850_cfgchip_register_async3()
325 struct da8xx_cfgchip_mux_clk *mux; in of_da8xx_cfgchip_init_mux_clock() local
327 mux = da8xx_cfgchip_mux_clk_register(dev, info, regmap); in of_da8xx_cfgchip_init_mux_clock()
328 if (IS_ERR(mux)) in of_da8xx_cfgchip_init_mux_clock()
329 return PTR_ERR(mux); in of_da8xx_cfgchip_init_mux_clock()
331 return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, &mux->hw); in of_da8xx_cfgchip_init_mux_clock()
344 /* --- USB 2.0 PHY clock --- */
363 return clk_prepare(usb0->fck); in da8xx_usb0_clk48_prepare()
370 clk_unprepare(usb0->fck); in da8xx_usb0_clk48_unprepare()
380 * temporaily. It can be turned back off once the PLL is locked. in da8xx_usb0_clk48_enable()
382 clk_enable(usb0->fck); in da8xx_usb0_clk48_enable()
390 regmap_write_bits(usb0->regmap, CFGCHIP(2), mask, val); in da8xx_usb0_clk48_enable()
391 ret = regmap_read_poll_timeout(usb0->regmap, CFGCHIP(2), val, in da8xx_usb0_clk48_enable()
394 clk_disable(usb0->fck); in da8xx_usb0_clk48_enable()
405 regmap_write_bits(usb0->regmap, CFGCHIP(2), val, val); in da8xx_usb0_clk48_disable()
413 regmap_read(usb0->regmap, CFGCHIP(2), &val); in da8xx_usb0_clk48_is_enabled()
458 regmap_write_bits(usb0->regmap, CFGCHIP(2), mask, val); in da8xx_usb0_clk48_recalc_rate()
474 return regmap_write_bits(usb0->regmap, CFGCHIP(2), in da8xx_usb0_clk48_set_parent()
484 regmap_read(usb0->regmap, CFGCHIP(2), &val); in da8xx_usb0_clk48_get_parent()
519 return ERR_PTR(-ENOMEM); in da8xx_cfgchip_register_usb0_clk48()
526 usb0->hw.init = &init; in da8xx_cfgchip_register_usb0_clk48()
527 usb0->fck = fck_clk; in da8xx_cfgchip_register_usb0_clk48()
528 usb0->regmap = regmap; in da8xx_cfgchip_register_usb0_clk48()
530 ret = devm_clk_hw_register(dev, &usb0->hw); in da8xx_cfgchip_register_usb0_clk48()
537 /* --- USB 1.1 PHY clock --- */
551 return regmap_write_bits(usb1->regmap, CFGCHIP(2), in da8xx_usb1_clk48_set_parent()
561 regmap_read(usb1->regmap, CFGCHIP(2), &val); in da8xx_usb1_clk48_get_parent()
572 * da8xx_cfgchip_register_usb1_clk48 - Register a new USB 1.1 PHY clock
587 return ERR_PTR(-ENOMEM); in da8xx_cfgchip_register_usb1_clk48()
594 usb1->hw.init = &init; in da8xx_cfgchip_register_usb1_clk48()
595 usb1->regmap = regmap; in da8xx_cfgchip_register_usb1_clk48()
597 ret = devm_clk_hw_register(dev, &usb1->hw); in da8xx_cfgchip_register_usb1_clk48()
617 * should use device tree, so hard-coding the value (1) here. in da8xx_cfgchip_register_usb_phy_clk()
619 parent = clk_hw_get_parent_by_index(&usb0->hw, 1); in da8xx_cfgchip_register_usb_phy_clk()
621 clk_set_parent(usb0->hw.clk, parent->clk); in da8xx_cfgchip_register_usb_phy_clk()
631 * should use device tree, so hard-coding the value (0) here. in da8xx_cfgchip_register_usb_phy_clk()
633 parent = clk_hw_get_parent_by_index(&usb1->hw, 0); in da8xx_cfgchip_register_usb_phy_clk()
635 clk_set_parent(usb1->hw.clk, parent->clk); in da8xx_cfgchip_register_usb_phy_clk()
639 clk_hw_register_clkdev(&usb0->hw, "usb0_clk48", "da8xx-usb-phy"); in da8xx_cfgchip_register_usb_phy_clk()
640 clk_hw_register_clkdev(&usb1->hw, "usb1_clk48", "da8xx-usb-phy"); in da8xx_cfgchip_register_usb_phy_clk()
654 return -ENOMEM; in of_da8xx_usb_phy_clk_init()
656 clk_data->num = 2; in of_da8xx_usb_phy_clk_init()
660 if (PTR_ERR(usb0) == -EPROBE_DEFER) in of_da8xx_usb_phy_clk_init()
661 return -EPROBE_DEFER; in of_da8xx_usb_phy_clk_init()
666 clk_data->hws[0] = ERR_PTR(-ENOENT); in of_da8xx_usb_phy_clk_init()
668 clk_data->hws[0] = &usb0->hw; in of_da8xx_usb_phy_clk_init()
673 if (PTR_ERR(usb1) == -EPROBE_DEFER) in of_da8xx_usb_phy_clk_init()
674 return -EPROBE_DEFER; in of_da8xx_usb_phy_clk_init()
679 clk_data->hws[1] = ERR_PTR(-ENOENT); in of_da8xx_usb_phy_clk_init()
681 clk_data->hws[1] = &usb1->hw; in of_da8xx_usb_phy_clk_init()
687 /* --- platform device --- */
691 .compatible = "ti,da830-tbclksync",
695 .compatible = "ti,da830-div4p5ena",
699 .compatible = "ti,da850-async1-clksrc",
703 .compatible = "ti,da850-async3-clksrc",
707 .compatible = "ti,da830-usb-phy-clocks",
715 .name = "da830-tbclksync",
719 .name = "da830-div4p5ena",
723 .name = "da850-async1-clksrc",
727 .name = "da850-async3-clksrc",
731 .name = "da830-usb-phy-clks",
741 struct device *dev = &pdev->dev; in da8xx_cfgchip_probe()
742 struct da8xx_cfgchip_clk_platform_data *pdata = dev->platform_data; in da8xx_cfgchip_probe()
751 clk_init = of_id->data; in da8xx_cfgchip_probe()
752 parent = of_get_parent(dev->of_node); in da8xx_cfgchip_probe()
755 } else if (pdev->id_entry && pdata) { in da8xx_cfgchip_probe()
756 clk_init = (void *)pdev->id_entry->driver_data; in da8xx_cfgchip_probe()
757 regmap = pdata->cfgchip; in da8xx_cfgchip_probe()
762 return -EINVAL; in da8xx_cfgchip_probe()
767 return regmap ? PTR_ERR(regmap) : -ENOENT; in da8xx_cfgchip_probe()
776 .name = "da8xx-cfgchip-clk",