Lines Matching refs:div_int
172 u32 div_int; member
434 u32 div_int, div_frc; in vc5_pll_recalc_rate() local
439 div_int = (fb[0] << 4) | (fb[1] >> 4); in vc5_pll_recalc_rate()
443 return (parent_rate * div_int) + ((parent_rate * div_frc) >> 24); in vc5_pll_recalc_rate()
450 u32 div_int; in vc5_pll_round_rate() local
459 div_int = rate / *parent_rate; in vc5_pll_round_rate()
460 if (div_int > 0xfff) in vc5_pll_round_rate()
468 hwdata->div_int = div_int; in vc5_pll_round_rate()
471 return (*parent_rate * div_int) + ((*parent_rate * div_frc) >> 24); in vc5_pll_round_rate()
481 fb[0] = hwdata->div_int >> 4; in vc5_pll_set_rate()
482 fb[1] = hwdata->div_int << 4; in vc5_pll_set_rate()
503 u32 div_int, div_frc; in vc5_fod_recalc_rate() local
512 div_int = (od_int[0] << 4) | (od_int[1] >> 4); in vc5_fod_recalc_rate()
517 if (div_int == 0 && div_frc == 0) in vc5_fod_recalc_rate()
521 return div64_u64((u64)f_in << 24ULL, ((u64)div_int << 24ULL) + div_frc); in vc5_fod_recalc_rate()
530 u32 div_int; in vc5_fod_round_rate() local
534 div_int = f_in / rate; in vc5_fod_round_rate()
540 if (div_int > 0xffe) { in vc5_fod_round_rate()
541 div_int = 0xffe; in vc5_fod_round_rate()
542 rate = f_in / div_int; in vc5_fod_round_rate()
550 hwdata->div_int = div_int; in vc5_fod_round_rate()
553 return div64_u64((u64)f_in << 24ULL, ((u64)div_int << 24ULL) + div_frc); in vc5_fod_round_rate()
566 hwdata->div_int >> 4, hwdata->div_int << 4, in vc5_fod_set_rate()