Lines Matching refs:div_frc

173 	u32			div_frc;  member
434 u32 div_int, div_frc; in vc5_pll_recalc_rate() local
440 div_frc = (fb[2] << 16) | (fb[3] << 8) | fb[4]; in vc5_pll_recalc_rate()
443 return (parent_rate * div_int) + ((parent_rate * div_frc) >> 24); in vc5_pll_recalc_rate()
451 u64 div_frc; in vc5_pll_round_rate() local
464 div_frc = rate % *parent_rate; in vc5_pll_round_rate()
465 div_frc *= BIT(24) - 1; in vc5_pll_round_rate()
466 do_div(div_frc, *parent_rate); in vc5_pll_round_rate()
469 hwdata->div_frc = (u32)div_frc; in vc5_pll_round_rate()
471 return (*parent_rate * div_int) + ((*parent_rate * div_frc) >> 24); in vc5_pll_round_rate()
483 fb[2] = hwdata->div_frc >> 16; in vc5_pll_set_rate()
484 fb[3] = hwdata->div_frc >> 8; in vc5_pll_set_rate()
485 fb[4] = hwdata->div_frc; in vc5_pll_set_rate()
503 u32 div_int, div_frc; in vc5_fod_recalc_rate() local
513 div_frc = (od_frc[0] << 22) | (od_frc[1] << 14) | in vc5_fod_recalc_rate()
517 if (div_int == 0 && div_frc == 0) in vc5_fod_recalc_rate()
521 return div64_u64((u64)f_in << 24ULL, ((u64)div_int << 24ULL) + div_frc); in vc5_fod_recalc_rate()
531 u64 div_frc; in vc5_fod_round_rate() local
546 div_frc = f_in % rate; in vc5_fod_round_rate()
547 div_frc <<= 24; in vc5_fod_round_rate()
548 do_div(div_frc, rate); in vc5_fod_round_rate()
551 hwdata->div_frc = (u32)div_frc; in vc5_fod_round_rate()
553 return div64_u64((u64)f_in << 24ULL, ((u64)div_int << 24ULL) + div_frc); in vc5_fod_round_rate()
562 hwdata->div_frc >> 22, hwdata->div_frc >> 14, in vc5_fod_set_rate()
563 hwdata->div_frc >> 6, hwdata->div_frc << 2, in vc5_fod_set_rate()