Lines Matching full:vc5
130 /* VC5 Input mux settings */
148 /* Supported IDT VC5 models. */
159 /* Structure to describe features of a particular VC5 model */
171 struct vc5_driver_data *vc5; member
179 struct vc5_driver_data *vc5; member
230 struct vc5_driver_data *vc5 = in vc5_mux_get_parent() local
236 ret = regmap_read(vc5->regmap, VC5_PRIM_SRC_SHDN, &src); in vc5_mux_get_parent()
248 dev_warn(&vc5->client->dev, in vc5_mux_get_parent()
255 struct vc5_driver_data *vc5 = in vc5_mux_set_parent() local
260 if ((index > 1) || !vc5->clk_mux_ins) in vc5_mux_set_parent()
263 if (vc5->clk_mux_ins == (VC5_MUX_IN_CLKIN | VC5_MUX_IN_XIN)) { in vc5_mux_set_parent()
272 if (vc5->clk_mux_ins == VC5_MUX_IN_XIN) in vc5_mux_set_parent()
274 else if (vc5->clk_mux_ins == VC5_MUX_IN_CLKIN) in vc5_mux_set_parent()
280 return regmap_update_bits(vc5->regmap, VC5_PRIM_SRC_SHDN, mask, src); in vc5_mux_set_parent()
291 struct vc5_driver_data *vc5 = in vc5_dbl_recalc_rate() local
296 ret = regmap_read(vc5->regmap, VC5_PRIM_SRC_SHDN, &premul); in vc5_dbl_recalc_rate()
318 struct vc5_driver_data *vc5 = in vc5_dbl_set_rate() local
327 return regmap_update_bits(vc5->regmap, VC5_PRIM_SRC_SHDN, in vc5_dbl_set_rate()
341 struct vc5_driver_data *vc5 = in vc5_pfd_recalc_rate() local
346 ret = regmap_read(vc5->regmap, VC5_VCO_CTRL_AND_PREDIV, &prediv); in vc5_pfd_recalc_rate()
354 ret = regmap_read(vc5->regmap, VC5_REF_DIVIDER, &div); in vc5_pfd_recalc_rate()
388 struct vc5_driver_data *vc5 = in vc5_pfd_set_rate() local
396 ret = regmap_set_bits(vc5->regmap, VC5_VCO_CTRL_AND_PREDIV, in vc5_pfd_set_rate()
401 return regmap_update_bits(vc5->regmap, VC5_REF_DIVIDER, 0xff, 0x00); in vc5_pfd_set_rate()
412 ret = regmap_update_bits(vc5->regmap, VC5_REF_DIVIDER, 0xff, div); in vc5_pfd_set_rate()
416 return regmap_clear_bits(vc5->regmap, VC5_VCO_CTRL_AND_PREDIV, in vc5_pfd_set_rate()
433 struct vc5_driver_data *vc5 = hwdata->vc5; in vc5_pll_recalc_rate() local
437 regmap_bulk_read(vc5->regmap, VC5_FEEDBACK_INT_DIV, fb, 5); in vc5_pll_recalc_rate()
478 struct vc5_driver_data *vc5 = hwdata->vc5; in vc5_pll_set_rate() local
487 return regmap_bulk_write(vc5->regmap, VC5_FEEDBACK_INT_DIV, fb, 5); in vc5_pll_set_rate()
500 struct vc5_driver_data *vc5 = hwdata->vc5; in vc5_fod_recalc_rate() local
507 regmap_bulk_read(vc5->regmap, VC5_OUT_DIV_INT(hwdata->num, 0), in vc5_fod_recalc_rate()
509 regmap_bulk_read(vc5->regmap, VC5_OUT_DIV_FRAC(hwdata->num, 0), in vc5_fod_recalc_rate()
560 struct vc5_driver_data *vc5 = hwdata->vc5; in vc5_fod_set_rate() local
571 ret = regmap_bulk_write(vc5->regmap, VC5_OUT_DIV_FRAC(hwdata->num, 0), in vc5_fod_set_rate()
582 ret = regmap_clear_bits(vc5->regmap, VC5_GLOBAL_REGISTER, in vc5_fod_set_rate()
587 return regmap_set_bits(vc5->regmap, VC5_GLOBAL_REGISTER, in vc5_fod_set_rate()
600 struct vc5_driver_data *vc5 = hwdata->vc5; in vc5_clk_out_prepare() local
615 if (vc5->chip_info->flags & VC5_HAS_BYPASS_SYNC_BIT) { in vc5_clk_out_prepare()
616 ret = regmap_set_bits(vc5->regmap, in vc5_clk_out_prepare()
627 ret = regmap_read(vc5->regmap, VC5_OUT_DIV_CONTROL(hwdata->num), &src); in vc5_clk_out_prepare()
633 ret = regmap_update_bits(vc5->regmap, in vc5_clk_out_prepare()
641 ret = regmap_set_bits(vc5->regmap, VC5_CLK_OUTPUT_CFG(hwdata->num, 1), in vc5_clk_out_prepare()
647 dev_dbg(&vc5->client->dev, "Update output %d mask 0x%0X val 0x%0X\n", in vc5_clk_out_prepare()
651 ret = regmap_update_bits(vc5->regmap, in vc5_clk_out_prepare()
665 struct vc5_driver_data *vc5 = hwdata->vc5; in vc5_clk_out_unprepare() local
668 regmap_clear_bits(vc5->regmap, VC5_CLK_OUTPUT_CFG(hwdata->num, 1), in vc5_clk_out_unprepare()
675 struct vc5_driver_data *vc5 = hwdata->vc5; in vc5_clk_out_get_parent() local
686 ret = regmap_read(vc5->regmap, VC5_OUT_DIV_CONTROL(hwdata->num), &src); in vc5_clk_out_get_parent()
701 dev_warn(&vc5->client->dev, in vc5_clk_out_get_parent()
709 struct vc5_driver_data *vc5 = hwdata->vc5; in vc5_clk_out_set_parent() local
723 return regmap_update_bits(vc5->regmap, VC5_OUT_DIV_CONTROL(hwdata->num), in vc5_clk_out_set_parent()
737 struct vc5_driver_data *vc5 = data; in vc5_of_clk_get() local
740 if (idx >= vc5->chip_info->clk_out_cnt) in vc5_of_clk_get()
743 return &vc5->clk_out[idx].hw; in vc5_of_clk_get()
848 static int vc5_update_cap_load(struct device_node *node, struct vc5_driver_data *vc5) in vc5_update_cap_load() argument
866 ret = regmap_update_bits(vc5->regmap, VC5_XTAL_X1_LOAD_CAP, ~0x03, in vc5_update_cap_load()
871 return regmap_update_bits(vc5->regmap, VC5_XTAL_X2_LOAD_CAP, ~0x03, in vc5_update_cap_load()
946 struct vc5_driver_data *vc5; in vc5_probe() local
952 vc5 = devm_kzalloc(&client->dev, sizeof(*vc5), GFP_KERNEL); in vc5_probe()
953 if (!vc5) in vc5_probe()
956 i2c_set_clientdata(client, vc5); in vc5_probe()
957 vc5->client = client; in vc5_probe()
958 vc5->chip_info = of_device_get_match_data(&client->dev); in vc5_probe()
960 vc5->pin_xin = devm_clk_get(&client->dev, "xin"); in vc5_probe()
961 if (PTR_ERR(vc5->pin_xin) == -EPROBE_DEFER) in vc5_probe()
964 vc5->pin_clkin = devm_clk_get(&client->dev, "clkin"); in vc5_probe()
965 if (PTR_ERR(vc5->pin_clkin) == -EPROBE_DEFER) in vc5_probe()
968 vc5->regmap = devm_regmap_init_i2c(client, &vc5_regmap_config); in vc5_probe()
969 if (IS_ERR(vc5->regmap)) in vc5_probe()
970 return dev_err_probe(&client->dev, PTR_ERR(vc5->regmap), in vc5_probe()
994 ret = regmap_update_bits(vc5->regmap, VC5_PRIM_SRC_SHDN, src_mask, in vc5_probe()
1002 if (!IS_ERR(vc5->pin_xin)) { in vc5_probe()
1003 vc5->clk_mux_ins |= VC5_MUX_IN_XIN; in vc5_probe()
1004 parent_names[init.num_parents++] = __clk_get_name(vc5->pin_xin); in vc5_probe()
1005 } else if (vc5->chip_info->flags & VC5_HAS_INTERNAL_XTAL) { in vc5_probe()
1006 vc5->pin_xin = clk_register_fixed_rate(&client->dev, in vc5_probe()
1009 if (IS_ERR(vc5->pin_xin)) in vc5_probe()
1010 return PTR_ERR(vc5->pin_xin); in vc5_probe()
1011 vc5->clk_mux_ins |= VC5_MUX_IN_XIN; in vc5_probe()
1012 parent_names[init.num_parents++] = __clk_get_name(vc5->pin_xin); in vc5_probe()
1015 if (!IS_ERR(vc5->pin_clkin)) { in vc5_probe()
1016 vc5->clk_mux_ins |= VC5_MUX_IN_CLKIN; in vc5_probe()
1018 __clk_get_name(vc5->pin_clkin); in vc5_probe()
1026 if (!(vc5->chip_info->flags & VC5_HAS_INTERNAL_XTAL)) { in vc5_probe()
1027 ret = vc5_update_cap_load(client->dev.of_node, vc5); in vc5_probe()
1036 vc5->clk_mux.init = &init; in vc5_probe()
1037 ret = devm_clk_hw_register(&client->dev, &vc5->clk_mux); in vc5_probe()
1042 if (vc5->chip_info->flags & VC5_HAS_PFD_FREQ_DBL) { in vc5_probe()
1050 parent_names[0] = clk_hw_get_name(&vc5->clk_mux); in vc5_probe()
1052 vc5->clk_mul.init = &init; in vc5_probe()
1053 ret = devm_clk_hw_register(&client->dev, &vc5->clk_mul); in vc5_probe()
1065 if (vc5->chip_info->flags & VC5_HAS_PFD_FREQ_DBL) in vc5_probe()
1066 parent_names[0] = clk_hw_get_name(&vc5->clk_mul); in vc5_probe()
1068 parent_names[0] = clk_hw_get_name(&vc5->clk_mux); in vc5_probe()
1070 vc5->clk_pfd.init = &init; in vc5_probe()
1071 ret = devm_clk_hw_register(&client->dev, &vc5->clk_pfd); in vc5_probe()
1082 parent_names[0] = clk_hw_get_name(&vc5->clk_pfd); in vc5_probe()
1084 vc5->clk_pll.num = 0; in vc5_probe()
1085 vc5->clk_pll.vc5 = vc5; in vc5_probe()
1086 vc5->clk_pll.hw.init = &init; in vc5_probe()
1087 ret = devm_clk_hw_register(&client->dev, &vc5->clk_pll.hw); in vc5_probe()
1093 for (n = 0; n < vc5->chip_info->clk_fod_cnt; n++) { in vc5_probe()
1094 idx = vc5_map_index_to_output(vc5->chip_info->model, n); in vc5_probe()
1101 parent_names[0] = clk_hw_get_name(&vc5->clk_pll.hw); in vc5_probe()
1103 vc5->clk_fod[n].num = idx; in vc5_probe()
1104 vc5->clk_fod[n].vc5 = vc5; in vc5_probe()
1105 vc5->clk_fod[n].hw.init = &init; in vc5_probe()
1106 ret = devm_clk_hw_register(&client->dev, &vc5->clk_fod[n].hw); in vc5_probe()
1119 parent_names[0] = clk_hw_get_name(&vc5->clk_mux); in vc5_probe()
1121 vc5->clk_out[0].num = idx; in vc5_probe()
1122 vc5->clk_out[0].vc5 = vc5; in vc5_probe()
1123 vc5->clk_out[0].hw.init = &init; in vc5_probe()
1124 ret = devm_clk_hw_register(&client->dev, &vc5->clk_out[0].hw); in vc5_probe()
1130 for (n = 1; n < vc5->chip_info->clk_out_cnt; n++) { in vc5_probe()
1131 idx = vc5_map_index_to_output(vc5->chip_info->model, n - 1); in vc5_probe()
1132 parent_names[0] = clk_hw_get_name(&vc5->clk_fod[idx].hw); in vc5_probe()
1134 parent_names[1] = clk_hw_get_name(&vc5->clk_mux); in vc5_probe()
1137 clk_hw_get_name(&vc5->clk_out[n - 1].hw); in vc5_probe()
1146 vc5->clk_out[n].num = idx; in vc5_probe()
1147 vc5->clk_out[n].vc5 = vc5; in vc5_probe()
1148 vc5->clk_out[n].hw.init = &init; in vc5_probe()
1149 ret = devm_clk_hw_register(&client->dev, &vc5->clk_out[n].hw); in vc5_probe()
1155 ret = vc5_get_output_config(client, &vc5->clk_out[n]); in vc5_probe()
1160 ret = of_clk_add_hw_provider(client->dev.of_node, vc5_of_clk_get, vc5); in vc5_probe()
1174 if (vc5->chip_info->flags & VC5_HAS_INTERNAL_XTAL) in vc5_probe()
1175 clk_unregister_fixed_rate(vc5->pin_xin); in vc5_probe()
1181 struct vc5_driver_data *vc5 = i2c_get_clientdata(client); in vc5_remove() local
1185 if (vc5->chip_info->flags & VC5_HAS_INTERNAL_XTAL) in vc5_remove()
1186 clk_unregister_fixed_rate(vc5->pin_xin); in vc5_remove()
1191 struct vc5_driver_data *vc5 = dev_get_drvdata(dev); in vc5_suspend() local
1193 regcache_cache_only(vc5->regmap, true); in vc5_suspend()
1194 regcache_mark_dirty(vc5->regmap); in vc5_suspend()
1201 struct vc5_driver_data *vc5 = dev_get_drvdata(dev); in vc5_resume() local
1204 regcache_cache_only(vc5->regmap, false); in vc5_resume()
1205 ret = regcache_sync(vc5->regmap); in vc5_resume()
1288 .name = "vc5",