Lines Matching +full:5 +full:p49v5923

3  * Driver for IDT Versaclock 5
96 #define VC5_CLK_OUTPUT_CFG0_CFG_SHIFT	5
124 #define VC5_GLOBAL_REGISTER_GLOBAL_RESET	BIT(5)
135 #define VC5_MAX_CLK_OUT_NUM	5
435 	u8 fb[5];  in vc5_pll_recalc_rate()
437 	regmap_bulk_read(vc5->regmap, VC5_FEEDBACK_INT_DIV, fb, 5);  in vc5_pll_recalc_rate()
479 	u8 fb[5];  in vc5_pll_set_rate()
487 	return regmap_bulk_write(vc5->regmap, VC5_FEEDBACK_INT_DIV, fb, 5);  in vc5_pll_set_rate()
820 	 * After getting feedback from Renesas, the .5pF steps were the  in vc5_map_cap_value()
828 	 * The Programmer's guide shows XTAL[5:0] but in reality,  in vc5_map_cap_value()
1221 	.clk_out_cnt = 5,
1235 	.clk_out_cnt = 5,
1242 	.clk_out_cnt = 5,
1249 	.clk_out_cnt = 5,
1256 	.clk_out_cnt = 5,
1261 	{ "5p49v5923", .driver_data = IDT_VC5_5P49V5923 },
1262 	{ "5p49v5925", .driver_data = IDT_VC5_5P49V5925 },
1263 	{ "5p49v5933", .driver_data = IDT_VC5_5P49V5933 },
1264 	{ "5p49v5935", .driver_data = IDT_VC5_5P49V5935 },
1265 	{ "5p49v6901", .driver_data = IDT_VC6_5P49V6901 },
1266 	{ "5p49v6965", .driver_data = IDT_VC6_5P49V6965 },
1267 	{ "5p49v6975", .driver_data = IDT_VC6_5P49V6975 },
1273 	{ .compatible = "idt,5p49v5923", .data = &idt_5p49v5923_info },
1274 	{ .compatible = "idt,5p49v5925", .data = &idt_5p49v5925_info },
1275 	{ .compatible = "idt,5p49v5933", .data = &idt_5p49v5933_info },
1276 	{ .compatible = "idt,5p49v5935", .data = &idt_5p49v5935_info },
1277 	{ .compatible = "idt,5p49v6901", .data = &idt_5p49v6901_info },
1278 	{ .compatible = "idt,5p49v6965", .data = &idt_5p49v6965_info },
1279 	{ .compatible = "idt,5p49v6975", .data = &idt_5p49v6975_info },
1299 MODULE_DESCRIPTION("IDT VersaClock 5 driver");