59 	struct clk_hw		clkin;  member
68 	"xtal", "clkin"
241  * Si5351 clkin clock input (Si5351C only)
246 		container_of(hw, struct si5351_driver_data, clkin);  in si5351_clkin_prepare()
255 		container_of(hw, struct si5351_driver_data, clkin);  in si5351_clkin_unprepare()
263  * If CLKIN is >40MHz, the input divider must be used.
269 		container_of(hw, struct si5351_driver_data, clkin);  in si5351_clkin_recalc_rate()
290 	dev_dbg(&drvdata->client->dev, "%s - clkin div = %d, rate = %lu\n",  in si5351_clkin_recalc_rate()
1406 	drvdata->pclkin = devm_clk_get(&client->dev, "clkin");  in si5351_i2c_probe()
1414 	 *   VARIANT_C can have CLKIN instead.  in si5351_i2c_probe()
1501 	/* register clkin input clock gate */  in si5351_i2c_probe()
1511 		drvdata->clkin.init = &init;  in si5351_i2c_probe()
1512 		ret = devm_clk_hw_register(&client->dev, &drvdata->clkin);  in si5351_i2c_probe()
1520 	/* Si5351C allows to mux either xtal or clkin to PLL input */  in si5351_i2c_probe()