Lines Matching +full:clk +full:- +full:div
1 // SPDX-License-Identifier: GPL-2.0-only
11 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
12 #include <linux/clk.h>
13 #include <linux/clk-provider.h>
33 #define CGA_PLL4 4 /* only on clockgen-1.0, which lacks CGB */
39 struct clk *clk; member
44 struct clockgen_pll_div div[MAX_PLL_DIV]; member
53 int div; /* PLL_DIVn */ member
82 int cmux_to_group[NUM_CMUX + 1]; /* array should be -1 terminated */
91 struct clk *sysclk, *coreclk;
93 struct clk *cmux[NUM_CMUX];
94 struct clk *hwaccel[NUM_HWACCEL];
95 struct clk *fman[2];
104 if (cg->info.flags & CG_LITTLE_ENDIAN) in cg_out()
114 if (cg->info.flags & CG_LITTLE_ENDIAN) in cg_in()
473 reg = ioread32be(&cg->guts->rcwsr[7]); in p2041_init_periph()
476 cg->fman[0] = cg->pll[CGA_PLL2].div[PLL_DIV2].clk; in p2041_init_periph()
478 cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk; in p2041_init_periph()
485 reg = ioread32be(&cg->guts->rcwsr[7]); in p4080_init_periph()
488 cg->fman[0] = cg->pll[CGA_PLL3].div[PLL_DIV2].clk; in p4080_init_periph()
490 cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk; in p4080_init_periph()
493 cg->fman[1] = cg->pll[CGA_PLL3].div[PLL_DIV2].clk; in p4080_init_periph()
495 cg->fman[1] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk; in p4080_init_periph()
501 int div = PLL_DIV2; in p5020_init_periph() local
503 reg = ioread32be(&cg->guts->rcwsr[7]); in p5020_init_periph()
505 div = PLL_DIV4; in p5020_init_periph()
508 cg->fman[0] = cg->pll[CGA_PLL2].div[div].clk; in p5020_init_periph()
510 cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk; in p5020_init_periph()
516 int div = PLL_DIV2; in p5040_init_periph() local
518 reg = ioread32be(&cg->guts->rcwsr[7]); in p5040_init_periph()
520 div = PLL_DIV4; in p5040_init_periph()
523 cg->fman[0] = cg->pll[CGA_PLL3].div[div].clk; in p5040_init_periph()
525 cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk; in p5040_init_periph()
528 cg->fman[1] = cg->pll[CGA_PLL3].div[div].clk; in p5040_init_periph()
530 cg->fman[1] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk; in p5040_init_periph()
535 cg->fman[0] = cg->hwaccel[1]; in t1023_init_periph()
540 cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV1].clk; in t1040_init_periph()
545 cg->fman[0] = cg->hwaccel[0]; in t2080_init_periph()
550 cg->fman[0] = cg->hwaccel[3]; in t4240_init_periph()
551 cg->fman[1] = cg->hwaccel[4]; in t4240_init_periph()
556 .compat = "fsl,b4420-clockgen",
557 .guts_compat = "fsl,b4860-device-config",
566 0, 1, 1, 1, -1
574 .compat = "fsl,b4860-clockgen",
575 .guts_compat = "fsl,b4860-device-config",
584 0, 1, 1, 1, -1
592 .compat = "fsl,ls1021a-clockgen",
597 0, -1
603 .compat = "fsl,ls1028a-clockgen",
612 0, 0, 0, 0, -1
619 .compat = "fsl,ls1043a-clockgen",
628 0, -1
635 .compat = "fsl,ls1046a-clockgen",
644 0, -1
651 .compat = "fsl,ls1088a-clockgen",
659 0, 0, -1
666 .compat = "fsl,ls1012a-clockgen",
671 0, -1
676 .compat = "fsl,ls2080a-clockgen",
681 0, 0, 1, 1, -1
689 .compat = "fsl,lx2160a-clockgen",
694 0, 0, 0, 0, 1, 1, 1, 1, -1
702 .compat = "fsl,p2041-clockgen",
703 .guts_compat = "fsl,qoriq-device-config-1.0",
709 0, 0, 1, 1, -1
715 .compat = "fsl,p3041-clockgen",
716 .guts_compat = "fsl,qoriq-device-config-1.0",
722 0, 0, 1, 1, -1
728 .compat = "fsl,p4080-clockgen",
729 .guts_compat = "fsl,qoriq-device-config-1.0",
735 0, 0, 0, 0, 1, 1, 1, 1, -1
742 .compat = "fsl,p5020-clockgen",
743 .guts_compat = "fsl,qoriq-device-config-1.0",
749 0, 1, -1
755 .compat = "fsl,p5040-clockgen",
756 .guts_compat = "fsl,p5040-device-config",
762 0, 0, 1, 1, -1
768 .compat = "fsl,t1023-clockgen",
769 .guts_compat = "fsl,t1023-device-config",
778 0, 0, -1
784 .compat = "fsl,t1040-clockgen",
785 .guts_compat = "fsl,t1040-device-config",
791 0, 0, 0, 0, -1
798 .compat = "fsl,t2080-clockgen",
799 .guts_compat = "fsl,t2080-device-config",
808 0, -1
815 .compat = "fsl,t4240-clockgen",
816 .guts_compat = "fsl,t4240-device-config",
825 0, 0, 1, -1
854 if (idx >= hwc->num_parents) in mux_set_parent()
855 return -EINVAL; in mux_set_parent()
857 clksel = hwc->parent_to_clksel[idx]; in mux_set_parent()
858 cg_out(hwc->cg, (clksel << CLKSEL_SHIFT) & CLKSEL_MASK, hwc->reg); in mux_set_parent()
869 clksel = (cg_in(hwc->cg, hwc->reg) & CLKSEL_MASK) >> CLKSEL_SHIFT; in mux_get_parent()
871 ret = hwc->clksel_to_parent[clksel]; in mux_get_parent()
873 pr_err("%s: mux at %p has bad clksel\n", __func__, hwc->reg); in mux_get_parent()
897 int pll, div; in get_pll_div() local
899 if (!(hwc->info->clksel[idx].flags & CLKSEL_VALID)) in get_pll_div()
902 pll = hwc->info->clksel[idx].pll; in get_pll_div()
903 div = hwc->info->clksel[idx].div; in get_pll_div()
905 return &cg->pll[pll].div[div]; in get_pll_div()
908 static struct clk * __init create_mux_common(struct clockgen *cg, in create_mux_common()
917 struct clk *clk; in create_mux_common() local
918 const struct clockgen_pll_div *div; in create_mux_common() local
928 hwc->clksel_to_parent[i] = -1; in create_mux_common()
930 div = get_pll_div(cg, hwc, i); in create_mux_common()
931 if (!div) in create_mux_common()
934 rate = clk_get_rate(div->clk); in create_mux_common()
936 if (hwc->info->clksel[i].flags & CLKSEL_80PCT && in create_mux_common()
944 parent_names[j] = div->name; in create_mux_common()
945 hwc->parent_to_clksel[j] = i; in create_mux_common()
946 hwc->clksel_to_parent[i] = j; in create_mux_common()
953 init.num_parents = hwc->num_parents = j; in create_mux_common()
955 hwc->hw.init = &init; in create_mux_common()
956 hwc->cg = cg; in create_mux_common()
958 clk = clk_register(NULL, &hwc->hw); in create_mux_common()
959 if (IS_ERR(clk)) { in create_mux_common()
961 PTR_ERR(clk)); in create_mux_common()
966 return clk; in create_mux_common()
969 static struct clk * __init create_one_cmux(struct clockgen *cg, int idx) in create_one_cmux()
972 const struct clockgen_pll_div *div; in create_one_cmux() local
981 if (cg->info.flags & CG_VER3) in create_one_cmux()
982 hwc->reg = cg->regs + 0x70000 + 0x20 * idx; in create_one_cmux()
984 hwc->reg = cg->regs + 0x20 * idx; in create_one_cmux()
986 hwc->info = cg->info.cmux_groups[cg->info.cmux_to_group[idx]]; in create_one_cmux()
995 clksel = (cg_in(cg, hwc->reg) & CLKSEL_MASK) >> CLKSEL_SHIFT; in create_one_cmux()
996 div = get_pll_div(cg, hwc, clksel); in create_one_cmux()
997 if (!div) { in create_one_cmux()
1002 max_rate = clk_get_rate(div->clk); in create_one_cmux()
1006 plat_rate = clk_get_rate(cg->pll[PLATFORM_PLL].div[PLL_DIV1].clk); in create_one_cmux()
1008 if (cg->info.flags & CG_CMUX_GE_PLAT) in create_one_cmux()
1014 pct80_rate, "cg-cmux%d", idx); in create_one_cmux()
1017 static struct clk * __init create_one_hwaccel(struct clockgen *cg, int idx) in create_one_hwaccel()
1025 hwc->reg = cg->regs + 0x20 * idx + 0x10; in create_one_hwaccel()
1026 hwc->info = cg->info.hwaccel[idx]; in create_one_hwaccel()
1029 "cg-hwaccel%d", idx); in create_one_hwaccel()
1036 for (i = 0; i < ARRAY_SIZE(cg->cmux); i++) { in create_muxes()
1037 if (cg->info.cmux_to_group[i] < 0) in create_muxes()
1039 if (cg->info.cmux_to_group[i] >= in create_muxes()
1040 ARRAY_SIZE(cg->info.cmux_groups)) { in create_muxes()
1045 cg->cmux[i] = create_one_cmux(cg, i); in create_muxes()
1048 for (i = 0; i < ARRAY_SIZE(cg->hwaccel); i++) { in create_muxes()
1049 if (!cg->info.hwaccel[i]) in create_muxes()
1052 cg->hwaccel[i] = create_one_hwaccel(cg, i); in create_muxes()
1061 * contain a "clocks" property -- otherwise the input clocks may
1078 struct clk *clk; in core_mux_init() local
1088 clk = clockgen.cmux[idx]; in core_mux_init()
1090 rc = of_clk_add_provider(np, of_clk_src_simple_get, clk); in core_mux_init()
1092 pr_err("%s: Couldn't register clk provider for node %pOFn: %d\n", in core_mux_init()
1098 static struct clk __init
1103 if (of_property_read_u32(node, "clock-frequency", &rate)) in sysclk_from_fixed()
1104 return ERR_PTR(-ENODEV); in sysclk_from_fixed()
1109 static struct clk __init *input_clock(const char *name, struct clk *clk) in input_clock() argument
1114 input_name = __clk_get_name(clk); in input_clock()
1115 clk = clk_register_fixed_factor(NULL, name, input_name, in input_clock()
1117 if (IS_ERR(clk)) in input_clock()
1119 PTR_ERR(clk)); in input_clock()
1121 return clk; in input_clock()
1124 static struct clk __init *input_clock_by_name(const char *name, in input_clock_by_name()
1127 struct clk *clk; in input_clock_by_name() local
1129 clk = of_clk_get_by_name(clockgen.node, dtname); in input_clock_by_name()
1130 if (IS_ERR(clk)) in input_clock_by_name()
1131 return clk; in input_clock_by_name()
1133 return input_clock(name, clk); in input_clock_by_name()
1136 static struct clk __init *input_clock_by_index(const char *name, int idx) in input_clock_by_index()
1138 struct clk *clk; in input_clock_by_index() local
1140 clk = of_clk_get(clockgen.node, 0); in input_clock_by_index()
1141 if (IS_ERR(clk)) in input_clock_by_index()
1142 return clk; in input_clock_by_index()
1144 return input_clock(name, clk); in input_clock_by_index()
1147 static struct clk * __init create_sysclk(const char *name) in create_sysclk()
1150 struct clk *clk; in create_sysclk() local
1152 clk = sysclk_from_fixed(clockgen.node, name); in create_sysclk()
1153 if (!IS_ERR(clk)) in create_sysclk()
1154 return clk; in create_sysclk()
1156 clk = input_clock_by_name(name, "sysclk"); in create_sysclk()
1157 if (!IS_ERR(clk)) in create_sysclk()
1158 return clk; in create_sysclk()
1160 clk = input_clock_by_index(name, 0); in create_sysclk()
1161 if (!IS_ERR(clk)) in create_sysclk()
1162 return clk; in create_sysclk()
1166 clk = sysclk_from_fixed(sysclk, name); in create_sysclk()
1168 if (!IS_ERR(clk)) in create_sysclk()
1169 return clk; in create_sysclk()
1176 static struct clk * __init create_coreclk(const char *name) in create_coreclk()
1178 struct clk *clk; in create_coreclk() local
1180 clk = input_clock_by_name(name, "coreclk"); in create_coreclk()
1181 if (!IS_ERR(clk)) in create_coreclk()
1182 return clk; in create_coreclk()
1190 if (WARN_ON(PTR_ERR(clk) == -EPROBE_DEFER)) in create_coreclk()
1191 return clk; in create_coreclk()
1199 struct clk *clk; in sysclk_init() local
1203 clk = clockgen.sysclk; in sysclk_init()
1204 if (clk) in sysclk_init()
1205 of_clk_add_provider(node, of_clk_src_simple_get, clk); in sysclk_init()
1214 struct clockgen_pll *pll = &cg->pll[idx]; in create_one_pll()
1215 const char *input = "cg-sysclk"; in create_one_pll()
1218 if (!(cg->info.pll_mask & (1 << idx))) in create_one_pll()
1221 if (cg->coreclk && idx != PLATFORM_PLL) { in create_one_pll()
1222 if (IS_ERR(cg->coreclk)) in create_one_pll()
1225 input = "cg-coreclk"; in create_one_pll()
1228 if (cg->info.flags & CG_VER3) { in create_one_pll()
1231 reg = cg->regs + 0x60080; in create_one_pll()
1234 reg = cg->regs + 0x80; in create_one_pll()
1237 reg = cg->regs + 0xa0; in create_one_pll()
1240 reg = cg->regs + 0x10080; in create_one_pll()
1243 reg = cg->regs + 0x100a0; in create_one_pll()
1251 reg = cg->regs + 0xc00; in create_one_pll()
1253 reg = cg->regs + 0x800 + 0x20 * (idx - 1); in create_one_pll()
1265 if ((cg->info.flags & CG_VER3) || in create_one_pll()
1266 ((cg->info.flags & CG_PLL_8BIT) && idx != PLATFORM_PLL)) in create_one_pll()
1271 for (i = 0; i < ARRAY_SIZE(pll->div); i++) { in create_one_pll()
1272 struct clk *clk; in create_one_pll() local
1282 snprintf(pll->div[i].name, sizeof(pll->div[i].name), in create_one_pll()
1283 "cg-pll%d-div%d", idx, i + 1); in create_one_pll()
1285 clk = clk_register_fixed_factor(NULL, in create_one_pll()
1286 pll->div[i].name, input, 0, mult, i + 1); in create_one_pll()
1287 if (IS_ERR(clk)) { in create_one_pll()
1289 __func__, pll->div[i].name, PTR_ERR(clk)); in create_one_pll()
1293 pll->div[i].clk = clk; in create_one_pll()
1294 ret = clk_register_clkdev(clk, pll->div[i].name, NULL); in create_one_pll()
1297 __func__, pll->div[i].name, ret); in create_one_pll()
1306 for (i = 0; i < ARRAY_SIZE(cg->pll); i++) in create_plls()
1314 struct clk **subclks; in legacy_pll_init()
1320 count = of_property_count_strings(np, "clock-output-names"); in legacy_pll_init()
1322 BUILD_BUG_ON(ARRAY_SIZE(pll->div) < 4); in legacy_pll_init()
1323 subclks = kcalloc(4, sizeof(struct clk *), GFP_KERNEL); in legacy_pll_init()
1332 subclks[0] = pll->div[0].clk; in legacy_pll_init()
1333 subclks[1] = pll->div[1].clk; in legacy_pll_init()
1334 subclks[2] = pll->div[3].clk; in legacy_pll_init()
1336 subclks[0] = pll->div[0].clk; in legacy_pll_init()
1337 subclks[1] = pll->div[1].clk; in legacy_pll_init()
1338 subclks[2] = pll->div[2].clk; in legacy_pll_init()
1339 subclks[3] = pll->div[3].clk; in legacy_pll_init()
1342 onecell_data->clks = subclks; in legacy_pll_init()
1343 onecell_data->clk_num = count; in legacy_pll_init()
1347 pr_err("%s: Couldn't register clk provider for node %pOFn: %d\n", in legacy_pll_init()
1386 static struct clk *clockgen_clk_get(struct of_phandle_args *clkspec, void *data) in clockgen_clk_get()
1389 struct clk *clk; in clockgen_clk_get() local
1393 if (clkspec->args_count < 2) { in clockgen_clk_get()
1395 return ERR_PTR(-EINVAL); in clockgen_clk_get()
1398 type = clkspec->args[0]; in clockgen_clk_get()
1399 idx = clkspec->args[1]; in clockgen_clk_get()
1405 clk = cg->sysclk; in clockgen_clk_get()
1408 if (idx >= ARRAY_SIZE(cg->cmux)) in clockgen_clk_get()
1410 clk = cg->cmux[idx]; in clockgen_clk_get()
1413 if (idx >= ARRAY_SIZE(cg->hwaccel)) in clockgen_clk_get()
1415 clk = cg->hwaccel[idx]; in clockgen_clk_get()
1418 if (idx >= ARRAY_SIZE(cg->fman)) in clockgen_clk_get()
1420 clk = cg->fman[idx]; in clockgen_clk_get()
1423 pll = &cg->pll[PLATFORM_PLL]; in clockgen_clk_get()
1424 if (idx >= ARRAY_SIZE(pll->div)) in clockgen_clk_get()
1426 clk = pll->div[idx].clk; in clockgen_clk_get()
1431 clk = cg->coreclk; in clockgen_clk_get()
1432 if (IS_ERR(clk)) in clockgen_clk_get()
1433 clk = NULL; in clockgen_clk_get()
1439 if (!clk) in clockgen_clk_get()
1440 return ERR_PTR(-ENOENT); in clockgen_clk_get()
1441 return clk; in clockgen_clk_get()
1445 return ERR_PTR(-EINVAL); in clockgen_clk_get()
1516 !strcmp(chipinfo[i].compat, "fsl,ls1021a-clockgen")) in _clockgen_init()
1545 clockgen.sysclk = create_sysclk("cg-sysclk"); in _clockgen_init()
1546 clockgen.coreclk = create_coreclk("cg-coreclk"); in _clockgen_init()
1555 pr_err("%s: Couldn't register clk provider for node %pOFn: %d\n", in _clockgen_init()
1578 pdev = platform_device_register_simple("qoriq-cpufreq", -1, in clockgen_cpufreq_init()
1581 pr_err("Couldn't register qoriq-cpufreq err=%ld\n", in clockgen_cpufreq_init()
1588 CLK_OF_DECLARE(qoriq_clockgen_1, "fsl,qoriq-clockgen-1.0", clockgen_init);
1589 CLK_OF_DECLARE(qoriq_clockgen_2, "fsl,qoriq-clockgen-2.0", clockgen_init);
1590 CLK_OF_DECLARE(qoriq_clockgen_b4420, "fsl,b4420-clockgen", clockgen_init);
1591 CLK_OF_DECLARE(qoriq_clockgen_b4860, "fsl,b4860-clockgen", clockgen_init);
1592 CLK_OF_DECLARE(qoriq_clockgen_ls1012a, "fsl,ls1012a-clockgen", clockgen_init);
1593 CLK_OF_DECLARE(qoriq_clockgen_ls1021a, "fsl,ls1021a-clockgen", clockgen_init);
1594 CLK_OF_DECLARE(qoriq_clockgen_ls1028a, "fsl,ls1028a-clockgen", clockgen_init);
1595 CLK_OF_DECLARE(qoriq_clockgen_ls1043a, "fsl,ls1043a-clockgen", clockgen_init);
1596 CLK_OF_DECLARE(qoriq_clockgen_ls1046a, "fsl,ls1046a-clockgen", clockgen_init);
1597 CLK_OF_DECLARE(qoriq_clockgen_ls1088a, "fsl,ls1088a-clockgen", clockgen_init);
1598 CLK_OF_DECLARE(qoriq_clockgen_ls2080a, "fsl,ls2080a-clockgen", clockgen_init);
1599 CLK_OF_DECLARE(qoriq_clockgen_lx2160a, "fsl,lx2160a-clockgen", clockgen_init);
1600 CLK_OF_DECLARE(qoriq_clockgen_p2041, "fsl,p2041-clockgen", clockgen_init);
1601 CLK_OF_DECLARE(qoriq_clockgen_p3041, "fsl,p3041-clockgen", clockgen_init);
1602 CLK_OF_DECLARE(qoriq_clockgen_p4080, "fsl,p4080-clockgen", clockgen_init);
1603 CLK_OF_DECLARE(qoriq_clockgen_p5020, "fsl,p5020-clockgen", clockgen_init);
1604 CLK_OF_DECLARE(qoriq_clockgen_p5040, "fsl,p5040-clockgen", clockgen_init);
1605 CLK_OF_DECLARE(qoriq_clockgen_t1023, "fsl,t1023-clockgen", clockgen_init);
1606 CLK_OF_DECLARE(qoriq_clockgen_t1040, "fsl,t1040-clockgen", clockgen_init);
1607 CLK_OF_DECLARE(qoriq_clockgen_t2080, "fsl,t2080-clockgen", clockgen_init);
1608 CLK_OF_DECLARE(qoriq_clockgen_t4240, "fsl,t4240-clockgen", clockgen_init);
1611 CLK_OF_DECLARE(qoriq_sysclk_1, "fsl,qoriq-sysclk-1.0", sysclk_init);
1612 CLK_OF_DECLARE(qoriq_sysclk_2, "fsl,qoriq-sysclk-2.0", sysclk_init);
1613 CLK_OF_DECLARE(qoriq_core_pll_1, "fsl,qoriq-core-pll-1.0", core_pll_init);
1614 CLK_OF_DECLARE(qoriq_core_pll_2, "fsl,qoriq-core-pll-2.0", core_pll_init);
1615 CLK_OF_DECLARE(qoriq_core_mux_1, "fsl,qoriq-core-mux-1.0", core_mux_init);
1616 CLK_OF_DECLARE(qoriq_core_mux_2, "fsl,qoriq-core-mux-2.0", core_mux_init);
1617 CLK_OF_DECLARE(qoriq_pltfrm_pll_1, "fsl,qoriq-platform-pll-1.0", pltfrm_pll_init);
1618 CLK_OF_DECLARE(qoriq_pltfrm_pll_2, "fsl,qoriq-platform-pll-2.0", pltfrm_pll_init);