Lines Matching +full:sysref +full:- +full:mux
1 // SPDX-License-Identifier: GPL-2.0
3 * LMK04832 Ultra Low-Noise JESD204B Compliant Clock Jitter Cleaner
14 #include <linux/clk-provider.h>
24 /* 0x000 - 0x00d System Functions */
36 /* 0x100 - 0x137 Device Clock and SYSREF Clock Output Control */
77 /* 0x138 - 0x145 SYSREF, SYNC, and Device Config */
126 /* 0x146 - 0x14a CLKin Control */
136 /* 0x14b - 0x152 Holdover */
138 /* 0x153 - 0x15f PLL1 Configuration */
140 /* 0x160 - 0x16e PLL2 Configuration */
163 /* 0x16F - 0x555 Misc Registers */
180 * lmk04832_device_info - Holds static device information that is specific to
222 bool sysref; member
228 * struct lmk04832 - The LMK04832 device structure
233 * @sysref_mux: select SYSREF source
234 * @sysref_pulse_cnt: number of SYSREF pulses generated while not in continuous
236 * @sysref_ddly: SYSREF digital delay value
239 * @sclk: reference to the internal sysref clock (SCLK)
330 ret = regmap_read(lmk->regmap, LMK04832_REG_MAIN_PD, &tmp); in lmk04832_vco_is_enabled()
344 ret = regmap_update_bits(lmk->regmap, LMK04832_REG_PLL2_PD, in lmk04832_vco_prepare()
351 return regmap_update_bits(lmk->regmap, LMK04832_REG_MAIN_PD, in lmk04832_vco_prepare()
361 regmap_update_bits(lmk->regmap, LMK04832_REG_PLL2_PD, in lmk04832_vco_unprepare()
366 regmap_update_bits(lmk->regmap, LMK04832_REG_MAIN_PD, in lmk04832_vco_unprepare()
381 ret = regmap_read(lmk->regmap, LMK04832_REG_PLL2_MISC, &pll2_misc); in lmk04832_vco_recalc_rate()
387 ret = regmap_bulk_read(lmk->regmap, LMK04832_REG_PLL2_N_0, &tmp, 3); in lmk04832_vco_recalc_rate()
395 ret = regmap_bulk_read(lmk->regmap, LMK04832_REG_PLL2_R_MSB, &tmp, 2); in lmk04832_vco_recalc_rate()
409 * lmk04832_check_vco_ranges - Check requested VCO frequency against VCO ranges
421 struct spi_device *spi = to_spi_device(lmk->dev); in lmk04832_check_vco_ranges()
425 info = &lmk04832_device_info[spi_get_device_id(spi)->driver_data]; in lmk04832_check_vco_ranges()
427 if (mhz >= info->vco0_range[0] && mhz <= info->vco0_range[1]) in lmk04832_check_vco_ranges()
430 if (mhz >= info->vco1_range[0] && mhz <= info->vco1_range[1]) in lmk04832_check_vco_ranges()
433 dev_err(lmk->dev, "%lu Hz is out of VCO ranges\n", rate); in lmk04832_check_vco_ranges()
434 return -ERANGE; in lmk04832_check_vco_ranges()
438 * lmk04832_calc_pll2_params - Get PLL2 parameters used to set the VCO frequency
479 return -EINVAL; in lmk04832_calc_pll2_params()
481 return -EINVAL; in lmk04832_calc_pll2_params()
504 dev_err(lmk->dev, "PLL2 parameters out of range\n"); in lmk04832_vco_round_rate()
509 return -EINVAL; in lmk04832_vco_round_rate()
527 ret = regmap_update_bits(lmk->regmap, LMK04832_REG_VCO_OSCOUT, in lmk04832_vco_set_rate()
535 dev_err(lmk->dev, "failed to determine PLL2 parameters\n"); in lmk04832_vco_set_rate()
539 ret = regmap_update_bits(lmk->regmap, LMK04832_REG_PLL2_R_MSB, in lmk04832_vco_set_rate()
545 ret = regmap_write(lmk->regmap, LMK04832_REG_PLL2_R_LSB, in lmk04832_vco_set_rate()
550 ret = regmap_update_bits(lmk->regmap, LMK04832_REG_PLL2_MISC, in lmk04832_vco_set_rate()
560 ret = regmap_write(lmk->regmap, LMK04832_REG_PLL2_N_0, in lmk04832_vco_set_rate()
564 ret = regmap_write(lmk->regmap, LMK04832_REG_PLL2_N_1, in lmk04832_vco_set_rate()
569 return regmap_write(lmk->regmap, LMK04832_REG_PLL2_N_2, in lmk04832_vco_set_rate()
583 * lmk04832_register_vco - Initialize the internal VCO and clock distribution
592 init.name = "lmk-vco"; in lmk04832_register_vco()
593 parent_names[0] = __clk_get_name(lmk->oscin); in lmk04832_register_vco()
599 ret = regmap_update_bits(lmk->regmap, LMK04832_REG_VCO_OSCOUT, in lmk04832_register_vco()
606 ret = regmap_update_bits(lmk->regmap, LMK04832_REG_FB_CTRL, in lmk04832_register_vco()
616 ret = regmap_update_bits(lmk->regmap, LMK04832_REG_PLL2_MISC, in lmk04832_register_vco()
622 ret = regmap_write(lmk->regmap, LMK04832_REG_PLL2_LD, in lmk04832_register_vco()
630 lmk->vco.init = &init; in lmk04832_register_vco()
631 return devm_clk_hw_register(lmk->dev, &lmk->vco); in lmk04832_register_vco()
636 int dclk_div_adj[] = {0, 0, -2, -2, 0, 3, -1, 0}; in lmk04832_clkout_set_ddly()
645 ret = regmap_update_bits(lmk->regmap, in lmk04832_clkout_set_ddly()
652 ret = regmap_read(lmk->regmap, LMK04832_REG_SYSREF_DDLY_LSB, &lsb); in lmk04832_clkout_set_ddly()
656 ret = regmap_read(lmk->regmap, LMK04832_REG_SYSREF_DDLY_MSB, &msb); in lmk04832_clkout_set_ddly()
662 ret = regmap_read(lmk->regmap, LMK04832_REG_CLKOUT_CTRL0(id), &lsb); in lmk04832_clkout_set_ddly()
666 ret = regmap_read(lmk->regmap, LMK04832_REG_CLKOUT_CTRL2(id), &msb); in lmk04832_clkout_set_ddly()
672 ret = regmap_read(lmk->regmap, LMK04832_REG_CLKOUT_CTRL3(id), &lsb); in lmk04832_clkout_set_ddly()
678 dclkx_y_ddly = sysref_ddly + 1 - in lmk04832_clkout_set_ddly()
679 dclk_div_adj[dclkx_y_div < 6 ? dclkx_y_div : 7] - in lmk04832_clkout_set_ddly()
683 dev_err(lmk->dev, "DCLKX_Y_DDLY out of range (%d)\n", in lmk04832_clkout_set_ddly()
685 return -EINVAL; in lmk04832_clkout_set_ddly()
688 ret = regmap_write(lmk->regmap, in lmk04832_clkout_set_ddly()
694 ret = regmap_write(lmk->regmap, LMK04832_REG_CLKOUT_CTRL1(id), in lmk04832_clkout_set_ddly()
699 dev_dbg(lmk->dev, "clkout%02u: sysref_ddly=%u, dclkx_y_ddly=%u, " in lmk04832_clkout_set_ddly()
705 return regmap_update_bits(lmk->regmap, LMK04832_REG_CLKOUT_CTRL2(id), in lmk04832_clkout_set_ddly()
710 /** lmk04832_sclk_sync - Establish deterministic phase relationship between sclk
716 * - in the datasheet https://www.ti.com/lit/ds/symlink/lmk04832.pdf, p.31
717 * (8.3.3.1 How to enable SYSREF)
718 * - Ti forum: https://e2e.ti.com/support/clock-and-timing/f/48/t/970972
729 ret = regmap_update_bits(lmk->regmap, LMK04832_REG_MAIN_PD, in lmk04832_sclk_sync_sequence()
735 for (i = 0; i < lmk->clk_data->num; i += 2) { in lmk04832_sclk_sync_sequence()
745 ret = regmap_update_bits(lmk->regmap, LMK04832_REG_SYSREF_OUT, in lmk04832_sclk_sync_sequence()
754 ret = regmap_update_bits(lmk->regmap, LMK04832_REG_SYNC, in lmk04832_sclk_sync_sequence()
762 ret = regmap_write(lmk->regmap, LMK04832_REG_SYNC_DIS, 0x00); in lmk04832_sclk_sync_sequence()
769 * PLL2-only use case, this will be complete in less than one SPI in lmk04832_sclk_sync_sequence()
770 * transaction. If SYSREF local digital delay is not used, this step in lmk04832_sclk_sync_sequence()
773 ret = regmap_update_bits(lmk->regmap, LMK04832_REG_SYNC, in lmk04832_sclk_sync_sequence()
779 ret = regmap_update_bits(lmk->regmap, LMK04832_REG_SYNC, in lmk04832_sclk_sync_sequence()
789 * does not shift into continuous SYSREF mode. in lmk04832_sclk_sync_sequence()
791 ret = regmap_update_bits(lmk->regmap, LMK04832_REG_SYNC, in lmk04832_sclk_sync_sequence()
797 ret = regmap_update_bits(lmk->regmap, LMK04832_REG_SYNC, in lmk04832_sclk_sync_sequence()
804 ret = regmap_write(lmk->regmap, LMK04832_REG_SYNC_DIS, 0xff); in lmk04832_sclk_sync_sequence()
809 ret = regmap_update_bits(lmk->regmap, LMK04832_REG_SYSREF_OUT, in lmk04832_sclk_sync_sequence()
812 lmk->sysref_mux)); in lmk04832_sclk_sync_sequence()
816 ret = regmap_update_bits(lmk->regmap, LMK04832_REG_SYNC, in lmk04832_sclk_sync_sequence()
819 lmk->sync_mode)); in lmk04832_sclk_sync_sequence()
824 * 9. (optional) if SCLKx_y_DIS_MODE was used to mute SYSREF outputs in lmk04832_sclk_sync_sequence()
846 ret = regmap_read(lmk->regmap, LMK04832_REG_MAIN_PD, &tmp); in lmk04832_sclk_is_enabled()
857 return regmap_update_bits(lmk->regmap, LMK04832_REG_MAIN_PD, in lmk04832_sclk_prepare()
865 regmap_update_bits(lmk->regmap, LMK04832_REG_MAIN_PD, in lmk04832_sclk_unprepare()
877 ret = regmap_bulk_read(lmk->regmap, LMK04832_REG_SYSREF_DIV_MSB, &tmp, 2); in lmk04832_sclk_recalc_rate()
898 dev_err(lmk->dev, "SYSREF divider out of range\n"); in lmk04832_sclk_round_rate()
899 return -EINVAL; in lmk04832_sclk_round_rate()
903 return -EINVAL; in lmk04832_sclk_round_rate()
918 dev_err(lmk->dev, "SYSREF divider out of range\n"); in lmk04832_sclk_set_rate()
919 return -EINVAL; in lmk04832_sclk_set_rate()
922 ret = regmap_write(lmk->regmap, LMK04832_REG_SYSREF_DIV_MSB, in lmk04832_sclk_set_rate()
927 ret = regmap_write(lmk->regmap, LMK04832_REG_SYSREF_DIV_LSB, in lmk04832_sclk_set_rate()
934 dev_err(lmk->dev, "SYNC sequence failed\n"); in lmk04832_sclk_set_rate()
954 init.name = "lmk-sclk"; in lmk04832_register_sclk()
955 parent_names[0] = clk_hw_get_name(&lmk->vco); in lmk04832_register_sclk()
962 ret = regmap_update_bits(lmk->regmap, LMK04832_REG_SYSREF_OUT, in lmk04832_register_sclk()
965 lmk->sysref_mux)); in lmk04832_register_sclk()
969 ret = regmap_write(lmk->regmap, LMK04832_REG_SYSREF_DDLY_LSB, in lmk04832_register_sclk()
970 FIELD_GET(0x00ff, lmk->sysref_ddly)); in lmk04832_register_sclk()
974 ret = regmap_write(lmk->regmap, LMK04832_REG_SYSREF_DDLY_MSB, in lmk04832_register_sclk()
975 FIELD_GET(0x1f00, lmk->sysref_ddly)); in lmk04832_register_sclk()
979 ret = regmap_write(lmk->regmap, LMK04832_REG_SYSREF_PULSE_CNT, in lmk04832_register_sclk()
980 ilog2(lmk->sysref_pulse_cnt)); in lmk04832_register_sclk()
984 ret = regmap_update_bits(lmk->regmap, LMK04832_REG_MAIN_PD, in lmk04832_register_sclk()
992 ret = regmap_write(lmk->regmap, LMK04832_REG_SYNC, in lmk04832_register_sclk()
995 FIELD_PREP(LMK04832_BIT_SYNC_MODE, lmk->sync_mode)); in lmk04832_register_sclk()
999 ret = regmap_write(lmk->regmap, LMK04832_REG_SYNC_DIS, 0xff); in lmk04832_register_sclk()
1003 lmk->sclk.init = &init; in lmk04832_register_sclk()
1004 return devm_clk_hw_register(lmk->dev, &lmk->sclk); in lmk04832_register_sclk()
1010 struct lmk04832 *lmk = dclk->lmk; in lmk04832_dclk_is_enabled()
1014 ret = regmap_read(lmk->regmap, LMK04832_REG_CLKOUT_CTRL3(dclk->id), in lmk04832_dclk_is_enabled()
1025 struct lmk04832 *lmk = dclk->lmk; in lmk04832_dclk_prepare()
1027 return regmap_update_bits(lmk->regmap, in lmk04832_dclk_prepare()
1028 LMK04832_REG_CLKOUT_CTRL3(dclk->id), in lmk04832_dclk_prepare()
1035 struct lmk04832 *lmk = dclk->lmk; in lmk04832_dclk_unprepare()
1037 regmap_update_bits(lmk->regmap, in lmk04832_dclk_unprepare()
1038 LMK04832_REG_CLKOUT_CTRL3(dclk->id), in lmk04832_dclk_unprepare()
1046 struct lmk04832 *lmk = dclk->lmk; in lmk04832_dclk_recalc_rate()
1052 ret = regmap_read(lmk->regmap, LMK04832_REG_CLKOUT_CTRL0(dclk->id), in lmk04832_dclk_recalc_rate()
1057 ret = regmap_read(lmk->regmap, LMK04832_REG_CLKOUT_CTRL2(dclk->id), in lmk04832_dclk_recalc_rate()
1072 struct lmk04832 *lmk = dclk->lmk; in lmk04832_dclk_round_rate()
1080 dev_err(lmk->dev, "%s_div out of range\n", clk_hw_get_name(hw)); in lmk04832_dclk_round_rate()
1081 return -EINVAL; in lmk04832_dclk_round_rate()
1085 return -EINVAL; in lmk04832_dclk_round_rate()
1094 struct lmk04832 *lmk = dclk->lmk; in lmk04832_dclk_set_rate()
1101 dev_err(lmk->dev, "%s_div out of range\n", clk_hw_get_name(hw)); in lmk04832_dclk_set_rate()
1102 return -EINVAL; in lmk04832_dclk_set_rate()
1107 ret = regmap_update_bits(lmk->regmap, in lmk04832_dclk_set_rate()
1108 LMK04832_REG_CLKOUT_CTRL3(dclk->id), in lmk04832_dclk_set_rate()
1116 * While using Divide-by-2 or Divide-by-3 for DCLK_X_Y_DIV, SYNC in lmk04832_dclk_set_rate()
1117 * procedure requires to first program Divide-by-4 and then back to in lmk04832_dclk_set_rate()
1118 * Divide-by-2 or Divide-by-3 before doing SYNC. in lmk04832_dclk_set_rate()
1121 ret = regmap_update_bits(lmk->regmap, in lmk04832_dclk_set_rate()
1122 LMK04832_REG_CLKOUT_CTRL2(dclk->id), in lmk04832_dclk_set_rate()
1127 ret = regmap_write(lmk->regmap, in lmk04832_dclk_set_rate()
1128 LMK04832_REG_CLKOUT_CTRL0(dclk->id), 0x04); in lmk04832_dclk_set_rate()
1133 ret = regmap_write(lmk->regmap, LMK04832_REG_CLKOUT_CTRL0(dclk->id), in lmk04832_dclk_set_rate()
1138 ret = regmap_update_bits(lmk->regmap, in lmk04832_dclk_set_rate()
1139 LMK04832_REG_CLKOUT_CTRL2(dclk->id), in lmk04832_dclk_set_rate()
1147 dev_err(lmk->dev, "SYNC sequence failed\n"); in lmk04832_dclk_set_rate()
1164 struct lmk04832 *lmk = clkout->lmk; in lmk04832_clkout_is_enabled()
1172 ret = regmap_read(lmk->regmap, LMK04832_REG_CLKOUT_CTRL2(clkout->id), in lmk04832_clkout_is_enabled()
1179 ret = regmap_read(lmk->regmap, LMK04832_REG_CLKOUT_SRC_MUX(clkout->id), in lmk04832_clkout_is_enabled()
1185 ret = regmap_read(lmk->regmap, in lmk04832_clkout_is_enabled()
1186 LMK04832_REG_CLKOUT_CTRL4(clkout->id), in lmk04832_clkout_is_enabled()
1194 ret = regmap_read(lmk->regmap, LMK04832_REG_CLKOUT_FMT(clkout->id), in lmk04832_clkout_is_enabled()
1199 if (clkout->id % 2) in lmk04832_clkout_is_enabled()
1210 struct lmk04832 *lmk = clkout->lmk; in lmk04832_clkout_prepare()
1214 if (clkout->format == LMK04832_VAL_CLKOUT_FMT_POWERDOWN) in lmk04832_clkout_prepare()
1215 dev_err(lmk->dev, "prepared %s but format is powerdown\n", in lmk04832_clkout_prepare()
1218 ret = regmap_update_bits(lmk->regmap, in lmk04832_clkout_prepare()
1219 LMK04832_REG_CLKOUT_CTRL2(clkout->id), in lmk04832_clkout_prepare()
1224 ret = regmap_read(lmk->regmap, LMK04832_REG_CLKOUT_SRC_MUX(clkout->id), in lmk04832_clkout_prepare()
1230 ret = regmap_update_bits(lmk->regmap, in lmk04832_clkout_prepare()
1231 LMK04832_REG_CLKOUT_CTRL4(clkout->id), in lmk04832_clkout_prepare()
1237 return regmap_update_bits(lmk->regmap, in lmk04832_clkout_prepare()
1238 LMK04832_REG_CLKOUT_FMT(clkout->id), in lmk04832_clkout_prepare()
1239 LMK04832_BIT_CLKOUT_FMT(clkout->id), in lmk04832_clkout_prepare()
1240 clkout->format << 4 * (clkout->id % 2)); in lmk04832_clkout_prepare()
1246 struct lmk04832 *lmk = clkout->lmk; in lmk04832_clkout_unprepare()
1248 regmap_update_bits(lmk->regmap, LMK04832_REG_CLKOUT_FMT(clkout->id), in lmk04832_clkout_unprepare()
1249 LMK04832_BIT_CLKOUT_FMT(clkout->id), in lmk04832_clkout_unprepare()
1256 struct lmk04832 *lmk = clkout->lmk; in lmk04832_clkout_set_parent()
1258 return regmap_update_bits(lmk->regmap, in lmk04832_clkout_set_parent()
1259 LMK04832_REG_CLKOUT_SRC_MUX(clkout->id), in lmk04832_clkout_set_parent()
1268 struct lmk04832 *lmk = clkout->lmk; in lmk04832_clkout_get_parent()
1272 ret = regmap_read(lmk->regmap, LMK04832_REG_CLKOUT_SRC_MUX(clkout->id), in lmk04832_clkout_get_parent()
1290 char name[] = "lmk-clkoutXX"; in lmk04832_register_clkout()
1291 char dclk_name[] = "lmk-dclkXX_YY"; in lmk04832_register_clkout()
1298 sprintf(dclk_name, "lmk-dclk%02d_%02d", num, num + 1); in lmk04832_register_clkout()
1300 parent_names[0] = clk_hw_get_name(&lmk->vco); in lmk04832_register_clkout()
1305 lmk->dclk[dclk_num].id = num; in lmk04832_register_clkout()
1306 lmk->dclk[dclk_num].lmk = lmk; in lmk04832_register_clkout()
1307 lmk->dclk[dclk_num].hw.init = &init; in lmk04832_register_clkout()
1309 ret = devm_clk_hw_register(lmk->dev, &lmk->dclk[dclk_num].hw); in lmk04832_register_clkout()
1313 sprintf(dclk_name, "lmk-dclk%02d_%02d", num - 1, num); in lmk04832_register_clkout()
1316 if (of_property_read_string_index(lmk->dev->of_node, in lmk04832_register_clkout()
1317 "clock-output-names", in lmk04832_register_clkout()
1319 sprintf(name, "lmk-clkout%02d", num); in lmk04832_register_clkout()
1324 parent_names[1] = clk_hw_get_name(&lmk->sclk); in lmk04832_register_clkout()
1330 lmk->clkout[num].id = num; in lmk04832_register_clkout()
1331 lmk->clkout[num].lmk = lmk; in lmk04832_register_clkout()
1332 lmk->clkout[num].hw.init = &init; in lmk04832_register_clkout()
1333 lmk->clk_data->hws[num] = &lmk->clkout[num].hw; in lmk04832_register_clkout()
1336 regmap_update_bits(lmk->regmap, in lmk04832_register_clkout()
1340 lmk->clkout[num].sysref)); in lmk04832_register_clkout()
1342 return devm_clk_hw_register(lmk->dev, &lmk->clkout[num].hw); in lmk04832_register_clkout()
1350 dev_info(lmk->dev, "setting up 4-wire mode\n"); in lmk04832_set_spi_rdbk()
1351 ret = regmap_write(lmk->regmap, LMK04832_REG_RST3W, in lmk04832_set_spi_rdbk()
1367 return -EINVAL; in lmk04832_set_spi_rdbk()
1370 return regmap_write(lmk->regmap, reg, in lmk04832_set_spi_rdbk()
1387 info = &lmk04832_device_info[spi_get_device_id(spi)->driver_data]; in lmk04832_probe()
1389 lmk = devm_kzalloc(&spi->dev, sizeof(struct lmk04832), GFP_KERNEL); in lmk04832_probe()
1391 return -ENOMEM; in lmk04832_probe()
1393 lmk->dev = &spi->dev; in lmk04832_probe()
1395 lmk->oscin = devm_clk_get(lmk->dev, "oscin"); in lmk04832_probe()
1396 if (IS_ERR(lmk->oscin)) { in lmk04832_probe()
1397 dev_err(lmk->dev, "failed to get oscin clock\n"); in lmk04832_probe()
1398 return PTR_ERR(lmk->oscin); in lmk04832_probe()
1401 ret = clk_prepare_enable(lmk->oscin); in lmk04832_probe()
1405 lmk->reset_gpio = devm_gpiod_get_optional(&spi->dev, "reset", in lmk04832_probe()
1408 lmk->dclk = devm_kcalloc(lmk->dev, info->num_channels >> 1, in lmk04832_probe()
1410 if (!lmk->dclk) { in lmk04832_probe()
1411 ret = -ENOMEM; in lmk04832_probe()
1415 lmk->clkout = devm_kcalloc(lmk->dev, info->num_channels, in lmk04832_probe()
1416 sizeof(*lmk->clkout), GFP_KERNEL); in lmk04832_probe()
1417 if (!lmk->clkout) { in lmk04832_probe()
1418 ret = -ENOMEM; in lmk04832_probe()
1422 lmk->clk_data = devm_kzalloc(lmk->dev, struct_size(lmk->clk_data, hws, in lmk04832_probe()
1423 info->num_channels), in lmk04832_probe()
1425 if (!lmk->clk_data) { in lmk04832_probe()
1426 ret = -ENOMEM; in lmk04832_probe()
1430 device_property_read_u32(lmk->dev, "ti,vco-hz", &lmk->vco_rate); in lmk04832_probe()
1432 lmk->sysref_ddly = 8; in lmk04832_probe()
1433 device_property_read_u32(lmk->dev, "ti,sysref-ddly", &lmk->sysref_ddly); in lmk04832_probe()
1435 lmk->sysref_mux = LMK04832_VAL_SYSREF_MUX_CONTINUOUS; in lmk04832_probe()
1436 device_property_read_u32(lmk->dev, "ti,sysref-mux", in lmk04832_probe()
1437 &lmk->sysref_mux); in lmk04832_probe()
1439 lmk->sync_mode = LMK04832_VAL_SYNC_MODE_OFF; in lmk04832_probe()
1440 device_property_read_u32(lmk->dev, "ti,sync-mode", in lmk04832_probe()
1441 &lmk->sync_mode); in lmk04832_probe()
1443 lmk->sysref_pulse_cnt = 4; in lmk04832_probe()
1444 device_property_read_u32(lmk->dev, "ti,sysref-pulse-count", in lmk04832_probe()
1445 &lmk->sysref_pulse_cnt); in lmk04832_probe()
1447 for_each_child_of_node(lmk->dev->of_node, child) { in lmk04832_probe()
1452 dev_err(lmk->dev, "missing reg property in child: %s\n", in lmk04832_probe()
1453 child->full_name); in lmk04832_probe()
1458 of_property_read_u32(child, "ti,clkout-fmt", in lmk04832_probe()
1459 &lmk->clkout[reg].format); in lmk04832_probe()
1461 if (lmk->clkout[reg].format >= 0x0a && reg % 2 == 0 in lmk04832_probe()
1463 dev_err(lmk->dev, "invalid format for clkout%02d\n", in lmk04832_probe()
1466 lmk->clkout[reg].sysref = in lmk04832_probe()
1467 of_property_read_bool(child, "ti,clkout-sysref"); in lmk04832_probe()
1470 lmk->regmap = devm_regmap_init_spi(spi, ®map_config); in lmk04832_probe()
1471 if (IS_ERR(lmk->regmap)) { in lmk04832_probe()
1472 dev_err(lmk->dev, "%s: regmap allocation failed: %ld\n", in lmk04832_probe()
1474 __func__, PTR_ERR(lmk->regmap)); in lmk04832_probe()
1475 ret = PTR_ERR(lmk->regmap); in lmk04832_probe()
1479 regmap_write(lmk->regmap, LMK04832_REG_RST3W, LMK04832_BIT_RESET); in lmk04832_probe()
1481 if (!(spi->mode & SPI_3WIRE)) { in lmk04832_probe()
1482 device_property_read_u32(lmk->dev, "ti,spi-4wire-rdbk", in lmk04832_probe()
1489 regmap_bulk_read(lmk->regmap, LMK04832_REG_ID_PROD_MSB, &tmp, 3); in lmk04832_probe()
1490 if ((tmp[0] << 8 | tmp[1]) != info->pid || tmp[2] != info->maskrev) { in lmk04832_probe()
1491 dev_err(lmk->dev, "unsupported device type: pid 0x%04x, maskrev 0x%02x\n", in lmk04832_probe()
1493 ret = -EINVAL; in lmk04832_probe()
1499 dev_err(lmk->dev, "failed to init device clock path\n"); in lmk04832_probe()
1503 if (lmk->vco_rate) { in lmk04832_probe()
1504 dev_info(lmk->dev, "setting VCO rate to %u Hz\n", lmk->vco_rate); in lmk04832_probe()
1505 ret = clk_set_rate(lmk->vco.clk, lmk->vco_rate); in lmk04832_probe()
1507 dev_err(lmk->dev, "failed to set VCO rate\n"); in lmk04832_probe()
1514 dev_err(lmk->dev, "failed to init SYNC/SYSREF clock path\n"); in lmk04832_probe()
1518 for (i = 0; i < info->num_channels; i++) { in lmk04832_probe()
1521 dev_err(lmk->dev, "failed to register clk %d\n", i); in lmk04832_probe()
1526 lmk->clk_data->num = info->num_channels; in lmk04832_probe()
1527 ret = of_clk_add_hw_provider(lmk->dev->of_node, of_clk_hw_onecell_get, in lmk04832_probe()
1528 lmk->clk_data); in lmk04832_probe()
1530 dev_err(lmk->dev, "failed to add provider (%d)\n", ret); in lmk04832_probe()
1539 clk_disable_unprepare(lmk->vco.clk); in lmk04832_probe()
1542 clk_disable_unprepare(lmk->oscin); in lmk04832_probe()
1551 clk_disable_unprepare(lmk->oscin); in lmk04832_remove()
1552 of_clk_del_provider(spi->dev.of_node); in lmk04832_remove()