Lines Matching full:oscin
237 * @oscin: PLL2 input clock
256 struct clk *oscin; member
440 * @prate: parent rate to the PLL2, usually OSCin
452 * VCO = OSCin * 2 * PLL2_N * PLL2_P / PLL2_R
593 parent_names[0] = __clk_get_name(lmk->oscin); in lmk04832_register_vco()
1395 lmk->oscin = devm_clk_get(lmk->dev, "oscin"); in lmk04832_probe()
1396 if (IS_ERR(lmk->oscin)) { in lmk04832_probe()
1397 dev_err(lmk->dev, "failed to get oscin clock\n"); in lmk04832_probe()
1398 return PTR_ERR(lmk->oscin); in lmk04832_probe()
1401 ret = clk_prepare_enable(lmk->oscin); in lmk04832_probe()
1542 clk_disable_unprepare(lmk->oscin); in lmk04832_probe()
1551 clk_disable_unprepare(lmk->oscin); in lmk04832_remove()