Lines Matching full:in0
341 * Set ACLK parent selector: 0 for IN0, 1 for PLL0.
399 * For PLL0, we need to re-parent ACLK to IN0 to keep the CPU cores and in k210_pll_enable_hw()
552 { /* .index = 0 for in0 */ }, in k210_register_pll()
576 /* PLL0 and PLL1 only have IN0 as parent */ in k210_register_plls()
588 /* PLL2 has IN0, PLL0 and PLL1 as parents */ in k210_register_plls()
644 * ACLK has IN0 and PLL0 as parents.
651 { /* .index = 0 for in0 */ }, in k210_register_aclk()
819 * All muxed clocks have IN0 and PLL0 as parents.
825 { /* .index = 0 for in0 */ }, in k210_register_mux_clk()
836 /* .index = 0 for in0 */ in k210_register_in0_child()
954 /* Clocks with IN0 as source */ in k210_clk_init()
971 /* Mux clocks with in0 or pll0 as source */ in k210_clk_init()