Lines Matching +full:50 +full:mhz
77 /* From dpll/epll/40mhz usb p1 phy/gpioc6/dp phy pll */
110 [ASPEED_CLK_GATE_UART3CLK] = { 50, -1, "uart3clk-gate", "uart", 0 }, /* UART3 */
182 /* F = 25Mhz * [(M + 2) / (n + 1)] / (p + 1) */ in ast2600_calc_pll()
202 /* F = 25Mhz * [(m + 1) / (n + 1)] / (p + 1) */ in ast2600_calc_apll()
215 /* F = 25Mhz * (2-od) * [(m + 2) / (n + 1)] */ in ast2600_calc_apll()
541 /* MAC1/2 RMII 50MHz RCLK */ in aspeed_g6_clk_probe()
555 /* RMII1 50MHz (RCLK) output enable */ in aspeed_g6_clk_probe()
563 /* RMII2 50MHz (RCLK) output enable */ in aspeed_g6_clk_probe()
571 /* MAC1/2 RMII 50MHz RCLK */ in aspeed_g6_clk_probe()
585 /* RMII3 50MHz (RCLK) output enable */ in aspeed_g6_clk_probe()
593 /* RMII4 50MHz (RCLK) output enable */ in aspeed_g6_clk_probe()
772 /* USB 2.0 port1 phy 40MHz clock */ in aspeed_g6_cc()