Lines Matching +full:4 +full:- +full:ch
1 // SPDX-License-Identifier: GPL-2.0
6 * Alexandre Belloni <alexandre.belloni@free-electrons.com>
8 #include <linux/clk-provider.h>
15 #include "berlin2-avpll.h"
19 * VCO with 8 channels each, channel 8 is the odd-one-out and does
34 /* BG2/BG2CDs VCO_B has an additional shift of 4 for its VCO_CTRL0 reg */
67 #define VCO_SPEED_1G86_2G00 VCO_SPEED(4)
118 reg = readl_relaxed(vco->base + VCO_CTRL0); in berlin2_avpll_vco_is_enabled()
119 if (vco->flags & BERLIN2_AVPLL_BIT_QUIRK) in berlin2_avpll_vco_is_enabled()
120 reg >>= 4; in berlin2_avpll_vco_is_enabled()
130 reg = readl_relaxed(vco->base + VCO_CTRL0); in berlin2_avpll_vco_enable()
131 if (vco->flags & BERLIN2_AVPLL_BIT_QUIRK) in berlin2_avpll_vco_enable()
132 reg |= VCO_POWERUP << 4; in berlin2_avpll_vco_enable()
135 writel_relaxed(reg, vco->base + VCO_CTRL0); in berlin2_avpll_vco_enable()
145 reg = readl_relaxed(vco->base + VCO_CTRL0); in berlin2_avpll_vco_disable()
146 if (vco->flags & BERLIN2_AVPLL_BIT_QUIRK) in berlin2_avpll_vco_disable()
147 reg &= ~(VCO_POWERUP << 4); in berlin2_avpll_vco_disable()
150 writel_relaxed(reg, vco->base + VCO_CTRL0); in berlin2_avpll_vco_disable()
153 static u8 vco_refdiv[] = { 1, 2, 4, 3 };
163 reg = readl_relaxed(vco->base + VCO_CTRL1); in berlin2_avpll_vco_recalc_rate()
189 return -ENOMEM; in berlin2_avpll_vco_register()
191 vco->base = base; in berlin2_avpll_vco_register()
192 vco->flags = vco_flags; in berlin2_avpll_vco_register()
193 vco->hw.init = &init; in berlin2_avpll_vco_register()
200 return clk_hw_register(NULL, &vco->hw); in berlin2_avpll_vco_register()
214 struct berlin2_avpll_channel *ch = to_avpll_channel(hw); in berlin2_avpll_channel_is_enabled() local
217 if (ch->index == 7) in berlin2_avpll_channel_is_enabled()
220 reg = readl_relaxed(ch->base + VCO_CTRL10); in berlin2_avpll_channel_is_enabled()
221 reg &= VCO_POWERUP_CH1 << ch->index; in berlin2_avpll_channel_is_enabled()
228 struct berlin2_avpll_channel *ch = to_avpll_channel(hw); in berlin2_avpll_channel_enable() local
231 reg = readl_relaxed(ch->base + VCO_CTRL10); in berlin2_avpll_channel_enable()
232 reg |= VCO_POWERUP_CH1 << ch->index; in berlin2_avpll_channel_enable()
233 writel_relaxed(reg, ch->base + VCO_CTRL10); in berlin2_avpll_channel_enable()
240 struct berlin2_avpll_channel *ch = to_avpll_channel(hw); in berlin2_avpll_channel_disable() local
243 reg = readl_relaxed(ch->base + VCO_CTRL10); in berlin2_avpll_channel_disable()
244 reg &= ~(VCO_POWERUP_CH1 << ch->index); in berlin2_avpll_channel_disable()
245 writel_relaxed(reg, ch->base + VCO_CTRL10); in berlin2_avpll_channel_disable()
248 static const u8 div_hdmi[] = { 1, 2, 4, 6 };
254 struct berlin2_avpll_channel *ch = to_avpll_channel(hw); in berlin2_avpll_channel_recalc_rate() local
258 reg = readl_relaxed(ch->base + VCO_CTRL30); in berlin2_avpll_channel_recalc_rate()
259 if ((reg & (VCO_DPLL_CH1_ENABLE << ch->index)) == 0) in berlin2_avpll_channel_recalc_rate()
267 reg = readl_relaxed(ch->base + VCO_SYNC1n(ch->index)); in berlin2_avpll_channel_recalc_rate()
268 /* BG2/BG2CDs SYNC1 reg on AVPLL_B channel 1 is shifted by 4 */ in berlin2_avpll_channel_recalc_rate()
269 if (ch->flags & BERLIN2_AVPLL_BIT_QUIRK && ch->index == 0) in berlin2_avpll_channel_recalc_rate()
270 reg >>= 4; in berlin2_avpll_channel_recalc_rate()
273 reg = readl_relaxed(ch->base + VCO_SYNC2n(ch->index)); in berlin2_avpll_channel_recalc_rate()
277 if (ch->index == 7) in berlin2_avpll_channel_recalc_rate()
284 reg = readl_relaxed(ch->base + VCO_CTRL11) >> 7; in berlin2_avpll_channel_recalc_rate()
285 reg = (reg >> (ch->index * 3)); in berlin2_avpll_channel_recalc_rate()
293 if (ch->index == 0) { in berlin2_avpll_channel_recalc_rate()
294 reg = readl_relaxed(ch->base + VCO_CTRL11); in berlin2_avpll_channel_recalc_rate()
297 reg = readl_relaxed(ch->base + VCO_CTRL12); in berlin2_avpll_channel_recalc_rate()
298 reg >>= (ch->index-1) * 3; in berlin2_avpll_channel_recalc_rate()
307 if (ch->index < 2) { in berlin2_avpll_channel_recalc_rate()
308 reg = readl_relaxed(ch->base + VCO_CTRL12); in berlin2_avpll_channel_recalc_rate()
309 reg >>= 18 + (ch->index * 7); in berlin2_avpll_channel_recalc_rate()
310 } else if (ch->index < 7) { in berlin2_avpll_channel_recalc_rate()
311 reg = readl_relaxed(ch->base + VCO_CTRL13); in berlin2_avpll_channel_recalc_rate()
312 reg >>= (ch->index - 2) * 7; in berlin2_avpll_channel_recalc_rate()
314 reg = readl_relaxed(ch->base + VCO_CTRL14); in berlin2_avpll_channel_recalc_rate()
321 * AV3 divider start at VCO_CTRL14, bit 7; each 4 bits wide. in berlin2_avpll_channel_recalc_rate()
325 if (ch->index < 6) { in berlin2_avpll_channel_recalc_rate()
326 reg = readl_relaxed(ch->base + VCO_CTRL14); in berlin2_avpll_channel_recalc_rate()
327 reg >>= 7 + (ch->index * 4); in berlin2_avpll_channel_recalc_rate()
329 reg = readl_relaxed(ch->base + VCO_CTRL15); in berlin2_avpll_channel_recalc_rate()
354 static const u8 quirk_index[] __initconst = { 0, 6, 5, 4, 3, 2, 1, 7 };
360 struct berlin2_avpll_channel *ch; in berlin2_avpll_channel_register() local
363 ch = kzalloc(sizeof(*ch), GFP_KERNEL); in berlin2_avpll_channel_register()
364 if (!ch) in berlin2_avpll_channel_register()
365 return -ENOMEM; in berlin2_avpll_channel_register()
367 ch->base = base; in berlin2_avpll_channel_register()
369 ch->index = quirk_index[index]; in berlin2_avpll_channel_register()
371 ch->index = index; in berlin2_avpll_channel_register()
373 ch->flags = ch_flags; in berlin2_avpll_channel_register()
374 ch->hw.init = &init; in berlin2_avpll_channel_register()
381 return clk_hw_register(NULL, &ch->hw); in berlin2_avpll_channel_register()