Lines Matching +full:8 +full:- +full:channel
1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
11 #include <dt-bindings/clock/bcm-nsp.h>
12 #include "clk-iproc.h"
33 CLK_OF_DECLARE(nsp_armpll, "brcm,nsp-armpll", nsp_armpll_init);
48 .channel = BCM_NSP_GENPLL_PHY_CLK,
51 .mdiv = REG_VAL(0x18, 16, 8),
54 .channel = BCM_NSP_GENPLL_ENET_SW_CLK,
57 .mdiv = REG_VAL(0x18, 8, 8),
60 .channel = BCM_NSP_GENPLL_USB_PHY_REF_CLK,
62 .enable = ENABLE_VAL(0x4, 14, 8, 20),
63 .mdiv = REG_VAL(0x18, 0, 8),
66 .channel = BCM_NSP_GENPLL_IPROCFAST_CLK,
69 .mdiv = REG_VAL(0x1c, 16, 8),
72 .channel = BCM_NSP_GENPLL_SATA1_CLK,
75 .mdiv = REG_VAL(0x1c, 8, 8),
78 .channel = BCM_NSP_GENPLL_SATA2_CLK,
81 .mdiv = REG_VAL(0x1c, 0, 8),
90 CLK_OF_DECLARE(nsp_genpll_clk, "brcm,nsp-genpll", nsp_genpll_clk_init);
97 .ndiv_int = REG_VAL(0x4, 20, 8),
105 .channel = BCM_NSP_LCPLL0_PCIE_PHY_REF_CLK,
108 .mdiv = REG_VAL(0x8, 24, 8),
111 .channel = BCM_NSP_LCPLL0_SDIO_CLK,
114 .mdiv = REG_VAL(0x8, 16, 8),
117 .channel = BCM_NSP_LCPLL0_DDR_PHY_CLK,
119 .enable = ENABLE_VAL(0x0, 8, 5, 11),
120 .mdiv = REG_VAL(0x8, 8, 8),
129 CLK_OF_DECLARE(nsp_lcpll0_clk, "brcm,nsp-lcpll0", nsp_lcpll0_clk_init);