40 #define CM_PASSWORD		0x5a000000
42 #define CM_GNRICCTL		0x000
43 #define CM_GNRICDIV		0x004
45 # define CM_DIV_FRAC_MASK	GENMASK(CM_DIV_FRAC_BITS - 1, 0)
47 #define CM_VPUCTL		0x008
48 #define CM_VPUDIV		0x00c
49 #define CM_SYSCTL		0x010
50 #define CM_SYSDIV		0x014
51 #define CM_PERIACTL		0x018
52 #define CM_PERIADIV		0x01c
53 #define CM_PERIICTL		0x020
54 #define CM_PERIIDIV		0x024
55 #define CM_H264CTL		0x028
56 #define CM_H264DIV		0x02c
57 #define CM_ISPCTL		0x030
58 #define CM_ISPDIV		0x034
59 #define CM_V3DCTL		0x038
60 #define CM_V3DDIV		0x03c
61 #define CM_CAM0CTL		0x040
62 #define CM_CAM0DIV		0x044
63 #define CM_CAM1CTL		0x048
64 #define CM_CAM1DIV		0x04c
65 #define CM_CCP2CTL		0x050
66 #define CM_CCP2DIV		0x054
67 #define CM_DSI0ECTL		0x058
68 #define CM_DSI0EDIV		0x05c
69 #define CM_DSI0PCTL		0x060
70 #define CM_DSI0PDIV		0x064
71 #define CM_DPICTL		0x068
72 #define CM_DPIDIV		0x06c
73 #define CM_GP0CTL		0x070
74 #define CM_GP0DIV		0x074
75 #define CM_GP1CTL		0x078
76 #define CM_GP1DIV		0x07c
77 #define CM_GP2CTL		0x080
78 #define CM_GP2DIV		0x084
79 #define CM_HSMCTL		0x088
80 #define CM_HSMDIV		0x08c
81 #define CM_OTPCTL		0x090
82 #define CM_OTPDIV		0x094
83 #define CM_PCMCTL		0x098
84 #define CM_PCMDIV		0x09c
85 #define CM_PWMCTL		0x0a0
86 #define CM_PWMDIV		0x0a4
87 #define CM_SLIMCTL		0x0a8
88 #define CM_SLIMDIV		0x0ac
89 #define CM_SMICTL		0x0b0
90 #define CM_SMIDIV		0x0b4
91 /* no definition for 0x0b8  and 0x0bc */
92 #define CM_TCNTCTL		0x0c0
94 #define CM_TCNTCNT		0x0c4
95 #define CM_TECCTL		0x0c8
96 #define CM_TECDIV		0x0cc
97 #define CM_TD0CTL		0x0d0
98 #define CM_TD0DIV		0x0d4
99 #define CM_TD1CTL		0x0d8
100 #define CM_TD1DIV		0x0dc
101 #define CM_TSENSCTL		0x0e0
102 #define CM_TSENSDIV		0x0e4
103 #define CM_TIMERCTL		0x0e8
104 #define CM_TIMERDIV		0x0ec
105 #define CM_UARTCTL		0x0f0
106 #define CM_UARTDIV		0x0f4
107 #define CM_VECCTL		0x0f8
108 #define CM_VECDIV		0x0fc
109 #define CM_PULSECTL		0x190
110 #define CM_PULSEDIV		0x194
111 #define CM_SDCCTL		0x1a8
112 #define CM_SDCDIV		0x1ac
113 #define CM_ARMCTL		0x1b0
114 #define CM_AVEOCTL		0x1b8
115 #define CM_AVEODIV		0x1bc
116 #define CM_EMMCCTL		0x1c0
117 #define CM_EMMCDIV		0x1c4
118 #define CM_EMMC2CTL		0x1d0
119 #define CM_EMMC2DIV		0x1d4
129 # define CM_SRC_SHIFT			0
131 # define CM_SRC_MASK			0xf
132 # define CM_SRC_GND			0
147 #define CM_OSCCOUNT		0x100
149 #define CM_PLLA			0x104
158 # define CM_PLLA_LOADDSI0		BIT(0)
160 #define CM_PLLC			0x108
168 # define CM_PLLC_LOADCORE0		BIT(0)
170 #define CM_PLLD			0x10c
178 # define CM_PLLD_LOADDSI0		BIT(0)
180 #define CM_PLLH			0x110
183 # define CM_PLLH_LOADPIX		BIT(0)
185 #define CM_LOCK			0x114
192 #define CM_EVENT		0x118
193 #define CM_DSI1ECTL		0x158
194 #define CM_DSI1EDIV		0x15c
195 #define CM_DSI1PCTL		0x160
196 #define CM_DSI1PDIV		0x164
197 #define CM_DFTCTL		0x168
198 #define CM_DFTDIV		0x16c
200 #define CM_PLLB			0x170
202 # define CM_PLLB_LOADARM		BIT(0)
204 #define A2W_PLLA_CTRL		0x1100
205 #define A2W_PLLC_CTRL		0x1120
206 #define A2W_PLLD_CTRL		0x1140
207 #define A2W_PLLH_CTRL		0x1160
208 #define A2W_PLLB_CTRL		0x11e0
211 # define A2W_PLL_CTRL_PDIV_MASK		0x000007000
213 # define A2W_PLL_CTRL_NDIV_MASK		0x0000003ff
214 # define A2W_PLL_CTRL_NDIV_SHIFT	0
216 #define A2W_PLLA_ANA0		0x1010
217 #define A2W_PLLC_ANA0		0x1030
218 #define A2W_PLLD_ANA0		0x1050
219 #define A2W_PLLH_ANA0		0x1070
220 #define A2W_PLLB_ANA0		0x10f0
233 #define A2W_PLLH_KI_HIGH_SHIFT	0
234 #define A2W_PLLH_KI_HIGH_MASK	GENMASK(0, 0)
238 #define A2W_XOSC_CTRL		0x1190
246 # define A2W_XOSC_CTRL_PLLC_ENABLE	BIT(0)
248 #define A2W_PLLA_FRAC		0x1200
249 #define A2W_PLLC_FRAC		0x1220
250 #define A2W_PLLD_FRAC		0x1240
251 #define A2W_PLLH_FRAC		0x1260
252 #define A2W_PLLB_FRAC		0x12e0
258 #define A2W_PLL_DIV_SHIFT		0
260 #define A2W_PLLA_DSI0		0x1300
261 #define A2W_PLLA_CORE		0x1400
262 #define A2W_PLLA_PER		0x1500
263 #define A2W_PLLA_CCP2		0x1600
265 #define A2W_PLLC_CORE2		0x1320
266 #define A2W_PLLC_CORE1		0x1420
267 #define A2W_PLLC_PER		0x1520
268 #define A2W_PLLC_CORE0		0x1620
270 #define A2W_PLLD_DSI0		0x1340
271 #define A2W_PLLD_CORE		0x1440
272 #define A2W_PLLD_PER		0x1540
273 #define A2W_PLLD_DSI1		0x1640
275 #define A2W_PLLH_AUX		0x1360
276 #define A2W_PLLH_RCAL		0x1460
277 #define A2W_PLLH_PIX		0x1560
278 #define A2W_PLLH_STS		0x1660
280 #define A2W_PLLH_CTRLR		0x1960
281 #define A2W_PLLH_FRACR		0x1a60
282 #define A2W_PLLH_AUXR		0x1b60
283 #define A2W_PLLH_RCALR		0x1c60
284 #define A2W_PLLH_PIXR		0x1d60
285 #define A2W_PLLH_STSR		0x1e60
287 #define A2W_PLLB_ARM		0x13e0
288 #define A2W_PLLB_SP0		0x14e0
289 #define A2W_PLLB_SP1		0x15e0
290 #define A2W_PLLB_SP2		0x16e0
295 #define SOC_BCM2835		BIT(0)
373 			count = 0;  in bcm2835_measure_tcnt_mux()
384 			count = 0;  in bcm2835_measure_tcnt_mux()
392 	cprman_write(cprman, CM_TCNTCTL, 0);  in bcm2835_measure_tcnt_mux()
450 	.mask0 = 0,
451 	.set0 = 0,
464 	.mask3 = 0,
465 	.set3 = 0,
542 		return 0;  in bcm2835_pll_get_prediv_mask()
565 	if (pdiv == 0)  in bcm2835_pll_rate_from_divisors()
566 		return 0;  in bcm2835_pll_rate_from_divisors()
597 	if (parent_rate == 0)  in bcm2835_pll_get_rate()
598 		return 0;  in bcm2835_pll_get_rate()
661 	return 0;  in bcm2835_pll_on()
677 	for (i = 3; i >= 0; i--)  in bcm2835_pll_write_ana()
702 	for (i = 3; i >= 0; i--)  in bcm2835_pll_set_rate()
707 	ana[0] &= ~data->ana->mask0;  in bcm2835_pll_set_rate()
708 	ana[0] |= data->ana->set0;  in bcm2835_pll_set_rate()
747 	return 0;  in bcm2835_pll_set_rate()
762 	regs[0].name = "cm_ctrl";  in bcm2835_pll_debug_init()
763 	regs[0].offset = data->cm_ctrl_reg;  in bcm2835_pll_debug_init()
769 	regs[3].offset = data->ana_reg_base + 0 * 4;  in bcm2835_pll_debug_init()
777 	bcm2835_debugfs_regset(cprman, 0, regs, 7, dentry);  in bcm2835_pll_debug_init()
854 	return 0;  in bcm2835_pll_divider_on()
870 		div = 0;  in bcm2835_pll_divider_set_rate()
877 	return 0;  in bcm2835_pll_divider_set_rate()
892 	regs[0].name = "cm";  in bcm2835_pll_divider_debug_init()
893 	regs[0].offset = data->cm_reg;  in bcm2835_pll_divider_debug_init()
897 	bcm2835_debugfs_regset(cprman, 0, regs, 2, dentry);  in bcm2835_pll_divider_debug_init()
933 	return (cprman_read(cprman, data->ctl_reg) & CM_ENABLE) != 0;  in bcm2835_clock_is_on()
943 		GENMASK(CM_DIV_FRAC_BITS - data->frac_bits, 0) >> 1;  in bcm2835_clock_choose_div()
979 	if (data->int_bits == 0 && data->frac_bits == 0)  in bcm2835_clock_rate_from_divisor()
989 	if (div == 0)  in bcm2835_clock_rate_from_divisor()
990 		return 0;  in bcm2835_clock_rate_from_divisor()
1014 	if ((rate + scaler - 1) / scaler % 1000 == 0)  in bcm2835_round_rate()
1029 	if (data->int_bits == 0 && data->frac_bits == 0)  in bcm2835_clock_get_rate()
1097 	return 0;  in bcm2835_clock_on()
1120 	ctl |= (div & CM_DIV_FRAC_MASK) ? CM_FRAC : 0;  in bcm2835_clock_set_rate()
1127 	return 0;  in bcm2835_clock_set_rate()
1136 	return strncmp(clk_hw_get_name(hw), "pllc", 4) == 0;  in bcm2835_clk_is_pllc()
1149 	unsigned long best_rate = 0;  in bcm2835_clock_choose_div_and_prate()
1214 	unsigned long rate, best_rate = 0;  in bcm2835_clock_determine_rate()
1215 	unsigned long prate, best_prate = 0;  in bcm2835_clock_determine_rate()
1216 	unsigned long avgrate, best_avgrate = 0;  in bcm2835_clock_determine_rate()
1225 	for (i = 0; i < clk_hw_get_num_parents(hw); ++i) {  in bcm2835_clock_determine_rate()
1259 	return 0;  in bcm2835_clock_determine_rate()
1270 	return 0;  in bcm2835_clock_set_parent()
1286 		.offset = 0,
1346 	memset(&init, 0, sizeof(init));  in bcm2835_register_pll()
1349 	init.parent_names = &cprman->real_parent_names[0];  in bcm2835_register_pll()
1390 	memset(&init, 0, sizeof(init));  in bcm2835_register_pll_divider()
1447 	for (i = 0; i < clock_data->num_mux_parents; i++) {  in bcm2835_register_clock()
1453 		if (ret >= 0)  in bcm2835_register_clock()
1457 	memset(&init, 0, sizeof(init));  in bcm2835_register_clock()
1506 				    CM_GATE_BIT, 0, &cprman->regs_lock);  in bcm2835_register_gate()
1912 		.hold_mask = 0,
1922 		.hold_mask = 0,
1932 		.hold_mask = 0,
1947 		.frac_bits = 0,
1970 		.frac_bits = 0),
1977 		.frac_bits = 0),
2007 		.frac_bits = 0,
2041 		.frac_bits = 0,
2065 		.frac_bits = 0),
2186 		.frac_bits = 0,
2216 		.int_bits = 0,
2217 		.frac_bits = 0,
2224 		.int_bits = 0,
2225 		.frac_bits = 0,
2285 	cprman->regs = devm_platform_ioremap_resource(pdev, 0);  in bcm2835_clk_probe()
2301 	if (!cprman->real_parent_names[0])  in bcm2835_clk_probe()
2310 	for (i = 0; i < asize; i++) {  in bcm2835_clk_probe()