Lines Matching full:eth_clk
143 CCU_DIV_VAR_INFO(CCU_AXI_GMAC0_CLK, "axi_gmac0_clk", "eth_clk",
146 CCU_DIV_VAR_INFO(CCU_AXI_GMAC1_CLK, "axi_gmac1_clk", "eth_clk",
149 CCU_DIV_VAR_INFO(CCU_AXI_XGMAC_CLK, "axi_xgmac_clk", "eth_clk",
164 CCU_DIV_VAR_INFO(CCU_AXI_SRAM_CLK, "axi_sram_clk", "eth_clk",
186 "eth_clk", CCU_SYS_GMAC0_BASE, 5),
188 "eth_clk", 10),
190 "eth_clk", CCU_SYS_GMAC1_BASE, 5),
192 "eth_clk", 10),
194 "eth_clk", CCU_SYS_XGMAC_BASE, 1),
200 "eth_clk", CCU_SYS_USB_BASE, 10),
208 "eth_clk", CCU_SYS_UART_BASE, 17,
211 "eth_clk", 10),
213 "eth_clk", 10),
226 "eth_clk", CCU_SYS_WDT_BASE, 17,