1 // SPDX-License-Identifier: GPL-2.0
3  * Copyright (C) 2018-2019 SiFive, Inc.
16  * pre-determined set of performance points.
19  * - Analog Bits "Wide Range PLL Datasheet", version 2015.10.01
20  * - SiFive FU540-C000 Manual v1p0, Chapter 7 "Clocking and Reset"
21  *   https://static.dev.sifive.com/FU540-C000-v1.0.pdf
32 #include <linux/clk/analogbits-wrpll-cln28hpc.h>
40 /* MIN_POST_DIVIDE_REF_FREQ: minimum post-divider reference frequency, in Hz */
43 /* MAX_POST_DIVIDE_REF_FREQ: maximum post-divider reference frequency, in Hz */
72  * __wrpll_calc_filter_range() - determine PLL loop filter bandwidth
76  * on the input clock frequency after the post-R-divider @post_divr_freq.
87 		WARN(1, "%s: post-divider reference freq out of range: %lu",  in __wrpll_calc_filter_range()
89 		return -ERANGE;  in __wrpll_calc_filter_range()
111  * __wrpll_calc_fbdiv() - return feedback fixed divide value
114  * The internal feedback path includes a fixed by-two divider; the
129 	return (c->flags & WRPLL_FLAGS_INT_FEEDBACK_MASK) ? 2 : 1;  in __wrpll_calc_fbdiv()
133  * __wrpll_calc_divq() - determine DIVQ based on target PLL output clock rate
137  * Determine a reasonable value for the PLL Q post-divider, based on the
175  * __wrpll_update_parent_rate() - update PLL data when parent rate changes
177  * @parent_rate: PLL input refclk rate (pre-R-divider)
179  * Pre-compute some data used by the PLL configuration algorithm when
181  * computation when the parent rate remains constant - expected to be
184  * Returns: 0 upon success or -ERANGE if the reference clock rate is
193 		return -ERANGE;  in __wrpll_update_parent_rate()
195 	c->parent_rate = parent_rate;  in __wrpll_update_parent_rate()
197 	c->max_r = min_t(u8, MAX_DIVR_DIVISOR, max_r_for_parent);  in __wrpll_update_parent_rate()
199 	c->init_r = DIV_ROUND_UP_ULL(parent_rate, MAX_POST_DIVR_FREQ);  in __wrpll_update_parent_rate()
205  * wrpll_configure_for_rate() - compute PLL configuration for a target rate
207  * @target_rate: target PLL output clock rate (post-Q-divider)
208  * @parent_rate: PLL input refclk rate (pre-R-divider)
213  * source or clock-gate it before presenting these values to the PLL
216  * The caller must pass this function a pre-initialized struct
234 	if (c->flags == 0) {  in wrpll_configure_for_rate()
236 		return -EINVAL;  in wrpll_configure_for_rate()
240 	if (parent_rate != c->parent_rate) {  in wrpll_configure_for_rate()
244 			return -ERANGE;  in wrpll_configure_for_rate()
248 	c->flags &= ~WRPLL_FLAGS_RESET_MASK;  in wrpll_configure_for_rate()
252 		c->flags |= WRPLL_FLAGS_BYPASS_MASK;  in wrpll_configure_for_rate()
256 	c->flags &= ~WRPLL_FLAGS_BYPASS_MASK;  in wrpll_configure_for_rate()
261 		return -1;  in wrpll_configure_for_rate()
262 	c->divq = divq;  in wrpll_configure_for_rate()
264 	/* Precalculate the pre-Q divider target ratio */  in wrpll_configure_for_rate()
276 	for (r = c->init_r; r <= c->max_r; ++r) {  in wrpll_configure_for_rate()
279 		f >>= (fbdiv - 1);  in wrpll_configure_for_rate()
287 			--f;  in wrpll_configure_for_rate()
294 		delta = abs(target_rate - vco);  in wrpll_configure_for_rate()
302 	c->divr = best_r - 1;  in wrpll_configure_for_rate()
303 	c->divf = best_f - 1;  in wrpll_configure_for_rate()
311 	c->range = range;  in wrpll_configure_for_rate()
317  * wrpll_calc_output_rate() - calculate the PLL's target output rate
323  * pre-divider), calculate the PLL's output clock rate (after the Q
324  * post-divider).
340 	if (c->flags & WRPLL_FLAGS_EXT_FEEDBACK_MASK) {  in wrpll_calc_output_rate()
346 	n = parent_rate * fbdiv * (c->divf + 1);  in wrpll_calc_output_rate()
347 	n = div_u64(n, c->divr + 1);  in wrpll_calc_output_rate()
348 	n >>= c->divq;  in wrpll_calc_output_rate()
354  * wrpll_calc_max_lock_us() - return the time for the PLL to lock