Lines Matching +full:bypass +full:- +full:attenuator +full:- +full:in

1 # SPDX-License-Identifier: GPL-2.0
16 	  Select this option when the clock API in <linux/clk.h> is implemented
31 	  implementation of the clock API in include/linux/clk.h.
60 	  Low-Noise JESD204B Compliant Clock Jitter Cleaner With Dual Loop PLLs
89 	  These multi-function devices have two fixed-rate oscillators, clocked at 32KHz each.
99 	  multi-function device has one fixed-rate oscillator, clocked
129 	  by the driver, in particular it only supports XTAL input. The chip can
130 	  be pre-programmed to support other configurations and features not yet
131 	  implemented in the driver.
179 	  This driver supports TI CDCE706 programmable 3-PLL clock synthesizer.
197 	  For example, the CDCE925 contains two PLLs with spread-spectrum
207 	tristate "Clock driver for CS2000 Fractional-N Clock Synthesizer & Clock Multiplier"
278 	  clock. These multi-function devices have two (S2MPS14) or three
279 	  (S2MPS11, S5M8767) fixed-rate oscillators, clocked at 32KHz each.
294 	  Support for the Analog Devices axi-clkgen pcore clock generator for Xilinx
295 	  FPGAs. It is commonly used in Analog Devices' reference designs.
313           configured bypass mode with this PLL.
320 	  Support for the APM X-Gene SoC reference, PLL, and device clocks.
363 	tristate "Clock driver for Renesas 9-series PCIe clock generators"
368 	  This driver supports the Renesas 9-series PCIe clock generator
387 	  and jitter attenuator ICs with fractional and integer dividers.
438 	  Support for the Canaan Kendryte K210 RISC-V SoC clocks.
442 source "drivers/clk/baikal-t1/Kconfig"
465 source "drivers/clk/sunxi-ng/Kconfig"