239 #define CHA     0x00   /* channel A offset */  macro
338 	if (channel == CHA) {  in irq_disable()
340 		write_reg16(info, CHA + IMR, info->imra_value);  in irq_disable()
348 	if (channel == CHA) {  in irq_enable()
350 		write_reg16(info, CHA + IMR, info->imra_value);  in irq_enable()
842 		issue_command(info, CHA, CMD_RXRESET);  in rx_ready_hdlc()
851 		fifo_count = (unsigned char)(read_reg(info, CHA+RBCL) & 0x1f);  in rx_ready_hdlc()
860 			data[0] = read_reg(info, CHA + RXFIFO);  in rx_ready_hdlc()
863 			*((unsigned short *) data) = read_reg16(info, CHA + RXFIFO);  in rx_ready_hdlc()
872 				issue_command(info, CHA, CMD_RXRESET);  in rx_ready_hdlc()
888 	issue_command(info, CHA, CMD_RXFIFO);  in rx_ready_hdlc()
901 		fifo_count = (unsigned char)(read_reg(info, CHA+RBCL) & 0x1f);  in rx_ready_async()
906 		if (!fifo_count && (read_reg(info,CHA+STAR) & BIT5))  in rx_ready_async()
914 		data   = read_reg(info, CHA + RXFIFO);  in rx_ready_async()
915 		status = read_reg(info, CHA + RXFIFO);  in rx_ready_async()
944 	issue_command(info, CHA, CMD_RXFIFO);  in rx_ready_async()
1023 			write_reg(info, CHA + TXFIFO, *(info->tx_buf + info->tx_get));  in tx_ready()
1025 			write_reg16(info, CHA + TXFIFO,  in tx_ready()
1036 		issue_command(info, CHA, CMD_TXFIFO);  in tx_ready()
1039 			issue_command(info, CHA, CMD_TXFIFO);  in tx_ready()
1041 			issue_command(info, CHA, CMD_TXFIFO + CMD_TXEOM);  in tx_ready()
1173 	while ((gis = read_reg(info, CHA + GIS))) {  in mgslpc_isr()
1192 			isr = read_reg16(info, CHA + ISR);  in mgslpc_isr()
1195 				irq_disable(info, CHA, IRQ_TIMER);  in mgslpc_isr()
1209 				issue_command(info, CHA, CMD_RXFIFO_READ);  in mgslpc_isr()
1234 			pis = read_reg(info, CHA + PIS);  in mgslpc_isr()
1986 		irq_enable(info, CHA, IRQ_EXITHUNT);  in wait_events()
2047 			irq_disable(info, CHA, IRQ_EXITHUNT);  in wait_events()
2178 		set_reg_bits(info, CHA+DAFO, BIT6);  in mgslpc_break()
2180 		clear_reg_bits(info, CHA+DAFO, BIT6);  in mgslpc_break()
2990 	val = read_reg(info, CHA + CCR1) | (BIT2 | BIT1 | BIT0);  in loopback_enable()
2991 	write_reg(info, CHA + CCR1, val);  in loopback_enable()
2994 	val = read_reg(info, CHA + CCR2) | (BIT4 | BIT5);  in loopback_enable()
2995 	write_reg(info, CHA + CCR2, val);  in loopback_enable()
2999 		mgslpc_set_rate(info, CHA, info->params.clock_speed);  in loopback_enable()
3001 		mgslpc_set_rate(info, CHA, 1843200);  in loopback_enable()
3004 	val = read_reg(info, CHA + MODE) | BIT0;  in loopback_enable()
3005 	write_reg(info, CHA + MODE, val);  in loopback_enable()
3014 	irq_disable(info, CHA, 0xffff);  in hdlc_mode()
3062 	write_reg(info, CHA + MODE, val);  in hdlc_mode()
3090 	write_reg(info, CHA + CCR0, val);  in hdlc_mode()
3104 	write_reg(info, CHA + CCR1, val);  in hdlc_mode()
3128 	write_reg(info, CHA + CCR2, val);  in hdlc_mode()
3159 	write_reg(info, CHA + CCR3, val);  in hdlc_mode()
3170 	write_reg(info, CHA + PRE, val);  in hdlc_mode()
3184 	write_reg(info, CHA + CCR4, val);  in hdlc_mode()
3186 		mgslpc_set_rate(info, CHA, info->params.clock_speed * 16);  in hdlc_mode()
3188 		mgslpc_set_rate(info, CHA, info->params.clock_speed);  in hdlc_mode()
3195 	write_reg(info, CHA + RLCR, 0);  in hdlc_mode()
3210 	write_reg(info, CHA + XBCH, val);  in hdlc_mode()
3218 		set_reg_bits(info, CHA + PVR, BIT3);  in hdlc_mode()
3220 		clear_reg_bits(info, CHA + PVR, BIT3);  in hdlc_mode()
3222 	irq_enable(info, CHA,  in hdlc_mode()
3225 	issue_command(info, CHA, CMD_TXRESET + CMD_RXRESET);  in hdlc_mode()
3226 	wait_command_complete(info, CHA);  in hdlc_mode()
3227 	read_reg16(info, CHA + ISR);	/* clear pending IRQs */  in hdlc_mode()
3240 		clear_reg_bits(info, CHA + CCR0, BIT6);  in hdlc_mode()
3255 	clear_reg_bits(info, CHA + MODE, BIT3);  in rx_stop()
3272 	set_reg_bits(info, CHA + MODE, BIT3);  in rx_start()
3332 	write_reg(info, CHA + CCR0, 0x80);  in reset_device()
3334 	write_reg(info, CHA + MODE, 0);  in reset_device()
3338 	irq_disable(info, CHA, 0xffff);  in reset_device()
3384 	irq_disable(info, CHA, 0xffff);  in async_mode()
3408 	write_reg(info, CHA + MODE, val);  in async_mode()
3420 	write_reg(info, CHA + CCR0, 0x83);  in async_mode()
3431 	write_reg(info, CHA + CCR1, 0x1f);  in async_mode()
3445 	write_reg(info, CHA + CCR2, 0x10);  in async_mode()
3454 	write_reg(info, CHA + CCR3, 0);  in async_mode()
3466 	write_reg(info, CHA + CCR4, 0x50);  in async_mode()
3467 	mgslpc_set_rate(info, CHA, info->params.data_rate * 16);  in async_mode()
3492 	write_reg(info, CHA + DAFO, val);  in async_mode()
3506 	write_reg(info, CHA + RFC, 0x5c);  in async_mode()
3512 	write_reg(info, CHA + RLCR, 0);  in async_mode()
3527 	write_reg(info, CHA + XBCH, val);  in async_mode()
3529 		irq_enable(info, CHA, IRQ_CTS);  in async_mode()
3532 	set_reg_bits(info, CHA + MODE, BIT3);  in async_mode()
3537 		set_reg_bits(info, CHA + PVR, BIT3);  in async_mode()
3539 		clear_reg_bits(info, CHA + PVR, BIT3);  in async_mode()
3540 	irq_enable(info, CHA,  in async_mode()
3543 	issue_command(info, CHA, CMD_TXRESET + CMD_RXRESET);  in async_mode()
3544 	wait_command_complete(info, CHA);  in async_mode()
3545 	read_reg16(info, CHA + ISR);	/* clear pending IRQs */  in async_mode()
3554 		set_reg_bits(info, CHA + CCR1, BIT3);  in tx_set_idle()
3556 		clear_reg_bits(info, CHA + CCR1, BIT3);  in tx_set_idle()
3573 	status = read_reg(info, CHA + PVR);  in get_signals()
3587 	val = read_reg(info, CHA + MODE);  in set_signals()
3599 	write_reg(info, CHA + MODE, val);  in set_signals()
3602 		clear_reg_bits(info, CHA + PVR, PVR_DTR);  in set_signals()
3604 		set_reg_bits(info, CHA + PVR, PVR_DTR);  in set_signals()
3751 	irq_enable(info, CHA, IRQ_TIMER);  in irq_test()
3752 	write_reg(info, CHA + TIMR, 0);	/* 512 cycles */  in irq_test()
3753 	issue_command(info, CHA, CMD_START_TIMER);  in irq_test()