Lines Matching +full:int +full:- +full:property
1 // SPDX-License-Identifier: GPL-2.0-only
53 static int tegra_gmi_enable(struct tegra_gmi *gmi) in tegra_gmi_enable()
55 int err; in tegra_gmi_enable()
57 pm_runtime_enable(gmi->dev); in tegra_gmi_enable()
58 err = pm_runtime_resume_and_get(gmi->dev); in tegra_gmi_enable()
60 pm_runtime_disable(gmi->dev); in tegra_gmi_enable()
64 reset_control_assert(gmi->rst); in tegra_gmi_enable()
66 reset_control_deassert(gmi->rst); in tegra_gmi_enable()
68 writel(gmi->snor_timing0, gmi->base + TEGRA_GMI_TIMING0); in tegra_gmi_enable()
69 writel(gmi->snor_timing1, gmi->base + TEGRA_GMI_TIMING1); in tegra_gmi_enable()
71 gmi->snor_config |= TEGRA_GMI_CONFIG_GO; in tegra_gmi_enable()
72 writel(gmi->snor_config, gmi->base + TEGRA_GMI_CONFIG); in tegra_gmi_enable()
82 config = readl(gmi->base + TEGRA_GMI_CONFIG); in tegra_gmi_disable()
84 writel(config, gmi->base + TEGRA_GMI_CONFIG); in tegra_gmi_disable()
86 reset_control_assert(gmi->rst); in tegra_gmi_disable()
88 pm_runtime_put_sync_suspend(gmi->dev); in tegra_gmi_disable()
89 pm_runtime_force_suspend(gmi->dev); in tegra_gmi_disable()
92 static int tegra_gmi_parse_dt(struct tegra_gmi *gmi) in tegra_gmi_parse_dt()
95 u32 property, ranges[4]; in tegra_gmi_parse_dt() local
96 int err; in tegra_gmi_parse_dt()
98 child = of_get_next_available_child(gmi->dev->of_node, NULL); in tegra_gmi_parse_dt()
100 dev_err(gmi->dev, "no child nodes found\n"); in tegra_gmi_parse_dt()
101 return -ENODEV; in tegra_gmi_parse_dt()
106 * chip-select address decoding. Which means that we only have one in tegra_gmi_parse_dt()
107 * chip-select line from the GMI controller. in tegra_gmi_parse_dt()
109 if (of_get_child_count(gmi->dev->of_node) > 1) in tegra_gmi_parse_dt()
110 dev_warn(gmi->dev, "only one child device is supported."); in tegra_gmi_parse_dt()
112 if (of_property_read_bool(child, "nvidia,snor-data-width-32bit")) in tegra_gmi_parse_dt()
113 gmi->snor_config |= TEGRA_GMI_BUS_WIDTH_32BIT; in tegra_gmi_parse_dt()
115 if (of_property_read_bool(child, "nvidia,snor-mux-mode")) in tegra_gmi_parse_dt()
116 gmi->snor_config |= TEGRA_GMI_MUX_MODE; in tegra_gmi_parse_dt()
118 if (of_property_read_bool(child, "nvidia,snor-rdy-active-before-data")) in tegra_gmi_parse_dt()
119 gmi->snor_config |= TEGRA_GMI_RDY_BEFORE_DATA; in tegra_gmi_parse_dt()
121 if (of_property_read_bool(child, "nvidia,snor-rdy-active-high")) in tegra_gmi_parse_dt()
122 gmi->snor_config |= TEGRA_GMI_RDY_ACTIVE_HIGH; in tegra_gmi_parse_dt()
124 if (of_property_read_bool(child, "nvidia,snor-adv-active-high")) in tegra_gmi_parse_dt()
125 gmi->snor_config |= TEGRA_GMI_ADV_ACTIVE_HIGH; in tegra_gmi_parse_dt()
127 if (of_property_read_bool(child, "nvidia,snor-oe-active-high")) in tegra_gmi_parse_dt()
128 gmi->snor_config |= TEGRA_GMI_OE_ACTIVE_HIGH; in tegra_gmi_parse_dt()
130 if (of_property_read_bool(child, "nvidia,snor-cs-active-high")) in tegra_gmi_parse_dt()
131 gmi->snor_config |= TEGRA_GMI_CS_ACTIVE_HIGH; in tegra_gmi_parse_dt()
137 if (err == -EOVERFLOW) { in tegra_gmi_parse_dt()
138 dev_err(gmi->dev, in tegra_gmi_parse_dt()
146 * CS# from the reg property instead. in tegra_gmi_parse_dt()
148 err = of_property_read_u32(child, "reg", &property); in tegra_gmi_parse_dt()
150 dev_err(gmi->dev, in tegra_gmi_parse_dt()
151 "failed to decode CS: no reg property found\n"); in tegra_gmi_parse_dt()
155 property = ranges[1]; in tegra_gmi_parse_dt()
158 /* Valid chip selects are CS0-CS7 */ in tegra_gmi_parse_dt()
159 if (property >= TEGRA_GMI_MAX_CHIP_SELECT) { in tegra_gmi_parse_dt()
160 dev_err(gmi->dev, "invalid chip select: %d", property); in tegra_gmi_parse_dt()
161 err = -EINVAL; in tegra_gmi_parse_dt()
165 gmi->snor_config |= TEGRA_GMI_CS_SELECT(property); in tegra_gmi_parse_dt()
168 if (!of_property_read_u32(child, "nvidia,snor-muxed-width", &property)) in tegra_gmi_parse_dt()
169 gmi->snor_timing0 |= TEGRA_GMI_MUXED_WIDTH(property); in tegra_gmi_parse_dt()
171 gmi->snor_timing0 |= TEGRA_GMI_MUXED_WIDTH(1); in tegra_gmi_parse_dt()
173 if (!of_property_read_u32(child, "nvidia,snor-hold-width", &property)) in tegra_gmi_parse_dt()
174 gmi->snor_timing0 |= TEGRA_GMI_HOLD_WIDTH(property); in tegra_gmi_parse_dt()
176 gmi->snor_timing0 |= TEGRA_GMI_HOLD_WIDTH(1); in tegra_gmi_parse_dt()
178 if (!of_property_read_u32(child, "nvidia,snor-adv-width", &property)) in tegra_gmi_parse_dt()
179 gmi->snor_timing0 |= TEGRA_GMI_ADV_WIDTH(property); in tegra_gmi_parse_dt()
181 gmi->snor_timing0 |= TEGRA_GMI_ADV_WIDTH(1); in tegra_gmi_parse_dt()
183 if (!of_property_read_u32(child, "nvidia,snor-ce-width", &property)) in tegra_gmi_parse_dt()
184 gmi->snor_timing0 |= TEGRA_GMI_CE_WIDTH(property); in tegra_gmi_parse_dt()
186 gmi->snor_timing0 |= TEGRA_GMI_CE_WIDTH(4); in tegra_gmi_parse_dt()
188 if (!of_property_read_u32(child, "nvidia,snor-we-width", &property)) in tegra_gmi_parse_dt()
189 gmi->snor_timing1 |= TEGRA_GMI_WE_WIDTH(property); in tegra_gmi_parse_dt()
191 gmi->snor_timing1 |= TEGRA_GMI_WE_WIDTH(1); in tegra_gmi_parse_dt()
193 if (!of_property_read_u32(child, "nvidia,snor-oe-width", &property)) in tegra_gmi_parse_dt()
194 gmi->snor_timing1 |= TEGRA_GMI_OE_WIDTH(property); in tegra_gmi_parse_dt()
196 gmi->snor_timing1 |= TEGRA_GMI_OE_WIDTH(1); in tegra_gmi_parse_dt()
198 if (!of_property_read_u32(child, "nvidia,snor-wait-width", &property)) in tegra_gmi_parse_dt()
199 gmi->snor_timing1 |= TEGRA_GMI_WAIT_WIDTH(property); in tegra_gmi_parse_dt()
201 gmi->snor_timing1 |= TEGRA_GMI_WAIT_WIDTH(3); in tegra_gmi_parse_dt()
208 static int tegra_gmi_probe(struct platform_device *pdev) in tegra_gmi_probe()
210 struct device *dev = &pdev->dev; in tegra_gmi_probe()
213 int err; in tegra_gmi_probe()
217 return -ENOMEM; in tegra_gmi_probe()
220 gmi->dev = dev; in tegra_gmi_probe()
223 gmi->base = devm_ioremap_resource(dev, res); in tegra_gmi_probe()
224 if (IS_ERR(gmi->base)) in tegra_gmi_probe()
225 return PTR_ERR(gmi->base); in tegra_gmi_probe()
227 gmi->clk = devm_clk_get(dev, "gmi"); in tegra_gmi_probe()
228 if (IS_ERR(gmi->clk)) { in tegra_gmi_probe()
230 return PTR_ERR(gmi->clk); in tegra_gmi_probe()
233 gmi->rst = devm_reset_control_get(dev, "gmi"); in tegra_gmi_probe()
234 if (IS_ERR(gmi->rst)) { in tegra_gmi_probe()
236 return PTR_ERR(gmi->rst); in tegra_gmi_probe()
239 err = devm_tegra_core_dev_init_opp_table_common(&pdev->dev); in tegra_gmi_probe()
251 err = of_platform_default_populate(dev->of_node, NULL, dev); in tegra_gmi_probe()
261 static int tegra_gmi_remove(struct platform_device *pdev) in tegra_gmi_remove()
265 of_platform_depopulate(gmi->dev); in tegra_gmi_remove()
271 static int __maybe_unused tegra_gmi_runtime_resume(struct device *dev) in tegra_gmi_runtime_resume()
274 int err; in tegra_gmi_runtime_resume()
276 err = clk_prepare_enable(gmi->clk); in tegra_gmi_runtime_resume()
278 dev_err(gmi->dev, "failed to enable clock: %d\n", err); in tegra_gmi_runtime_resume()
285 static int __maybe_unused tegra_gmi_runtime_suspend(struct device *dev) in tegra_gmi_runtime_suspend()
289 clk_disable_unprepare(gmi->clk); in tegra_gmi_runtime_suspend()
300 { .compatible = "nvidia,tegra20-gmi", },
301 { .compatible = "nvidia,tegra30-gmi", },
310 .name = "tegra-gmi",