95 	u32 property, ranges[4];  in tegra_gmi_parse_dt()  local
146 		 * CS# from the reg property instead.  in tegra_gmi_parse_dt()
148 		err = of_property_read_u32(child, "reg", &property);  in tegra_gmi_parse_dt()
151 				"failed to decode CS: no reg property found\n");  in tegra_gmi_parse_dt()
155 		property = ranges[1];  in tegra_gmi_parse_dt()
159 	if (property >= TEGRA_GMI_MAX_CHIP_SELECT) {  in tegra_gmi_parse_dt()
160 		dev_err(gmi->dev, "invalid chip select: %d", property);  in tegra_gmi_parse_dt()
165 	gmi->snor_config |= TEGRA_GMI_CS_SELECT(property);  in tegra_gmi_parse_dt()
168 	if (!of_property_read_u32(child, "nvidia,snor-muxed-width", &property))  in tegra_gmi_parse_dt()
169 		gmi->snor_timing0 |= TEGRA_GMI_MUXED_WIDTH(property);  in tegra_gmi_parse_dt()
173 	if (!of_property_read_u32(child, "nvidia,snor-hold-width", &property))  in tegra_gmi_parse_dt()
174 		gmi->snor_timing0 |= TEGRA_GMI_HOLD_WIDTH(property);  in tegra_gmi_parse_dt()
178 	if (!of_property_read_u32(child, "nvidia,snor-adv-width", &property))  in tegra_gmi_parse_dt()
179 		gmi->snor_timing0 |= TEGRA_GMI_ADV_WIDTH(property);  in tegra_gmi_parse_dt()
183 	if (!of_property_read_u32(child, "nvidia,snor-ce-width", &property))  in tegra_gmi_parse_dt()
184 		gmi->snor_timing0 |= TEGRA_GMI_CE_WIDTH(property);  in tegra_gmi_parse_dt()
188 	if (!of_property_read_u32(child, "nvidia,snor-we-width", &property))  in tegra_gmi_parse_dt()
189 		gmi->snor_timing1 |= TEGRA_GMI_WE_WIDTH(property);  in tegra_gmi_parse_dt()
193 	if (!of_property_read_u32(child, "nvidia,snor-oe-width", &property))  in tegra_gmi_parse_dt()
194 		gmi->snor_timing1 |= TEGRA_GMI_OE_WIDTH(property);  in tegra_gmi_parse_dt()
198 	if (!of_property_read_u32(child, "nvidia,snor-wait-width", &property))  in tegra_gmi_parse_dt()
199 		gmi->snor_timing1 |= TEGRA_GMI_WAIT_WIDTH(property);  in tegra_gmi_parse_dt()