87 	struct mhi_controller *mhi_cntrl = mhi_dev->mhi_cntrl;  in serial_number_show()  local
90 			mhi_cntrl->serial_number);  in serial_number_show()
99 	struct mhi_controller *mhi_cntrl = mhi_dev->mhi_cntrl;  in oem_pk_hash_show()  local
102 	for (i = 0; i < ARRAY_SIZE(mhi_cntrl->oem_pk_hash); i++)  in oem_pk_hash_show()
104 				i, mhi_cntrl->oem_pk_hash[i]);  in oem_pk_hash_show()
116 	struct mhi_controller *mhi_cntrl = mhi_dev->mhi_cntrl;  in soc_reset_store()  local
118 	mhi_soc_reset(mhi_cntrl);  in soc_reset_store()
132 static int mhi_alloc_aligned_ring(struct mhi_controller *mhi_cntrl,  in mhi_alloc_aligned_ring()  argument
137 	ring->pre_aligned = dma_alloc_coherent(mhi_cntrl->cntrl_dev, ring->alloc_size,  in mhi_alloc_aligned_ring()
148 void mhi_deinit_free_irq(struct mhi_controller *mhi_cntrl)  in mhi_deinit_free_irq()  argument
151 	struct mhi_event *mhi_event = mhi_cntrl->mhi_event;  in mhi_deinit_free_irq()
153 	for (i = 0; i < mhi_cntrl->total_ev_rings; i++, mhi_event++) {  in mhi_deinit_free_irq()
157 		free_irq(mhi_cntrl->irq[mhi_event->irq], mhi_event);  in mhi_deinit_free_irq()
160 	free_irq(mhi_cntrl->irq[0], mhi_cntrl);  in mhi_deinit_free_irq()
163 int mhi_init_irq_setup(struct mhi_controller *mhi_cntrl)  in mhi_init_irq_setup()  argument
165 	struct mhi_event *mhi_event = mhi_cntrl->mhi_event;  in mhi_init_irq_setup()
166 	struct device *dev = &mhi_cntrl->mhi_dev->dev;  in mhi_init_irq_setup()
171 	if (mhi_cntrl->irq_flags)  in mhi_init_irq_setup()
172 		irq_flags = mhi_cntrl->irq_flags;  in mhi_init_irq_setup()
175 	ret = request_threaded_irq(mhi_cntrl->irq[0], mhi_intvec_handler,  in mhi_init_irq_setup()
178 				   "bhi", mhi_cntrl);  in mhi_init_irq_setup()
186 	disable_irq(mhi_cntrl->irq[0]);  in mhi_init_irq_setup()
188 	for (i = 0; i < mhi_cntrl->total_ev_rings; i++, mhi_event++) {  in mhi_init_irq_setup()
192 		if (mhi_event->irq >= mhi_cntrl->nr_irqs) {  in mhi_init_irq_setup()
199 		ret = request_irq(mhi_cntrl->irq[mhi_event->irq],  in mhi_init_irq_setup()
205 				mhi_cntrl->irq[mhi_event->irq], i);  in mhi_init_irq_setup()
209 		disable_irq(mhi_cntrl->irq[mhi_event->irq]);  in mhi_init_irq_setup()
219 		free_irq(mhi_cntrl->irq[mhi_event->irq], mhi_event);  in mhi_init_irq_setup()
221 	free_irq(mhi_cntrl->irq[0], mhi_cntrl);  in mhi_init_irq_setup()
226 void mhi_deinit_dev_ctxt(struct mhi_controller *mhi_cntrl)  in mhi_deinit_dev_ctxt()  argument
229 	struct mhi_ctxt *mhi_ctxt = mhi_cntrl->mhi_ctxt;  in mhi_deinit_dev_ctxt()
234 	mhi_cmd = mhi_cntrl->mhi_cmd;  in mhi_deinit_dev_ctxt()
237 		dma_free_coherent(mhi_cntrl->cntrl_dev, ring->alloc_size,  in mhi_deinit_dev_ctxt()
243 	dma_free_coherent(mhi_cntrl->cntrl_dev,  in mhi_deinit_dev_ctxt()
247 	mhi_event = mhi_cntrl->mhi_event;  in mhi_deinit_dev_ctxt()
248 	for (i = 0; i < mhi_cntrl->total_ev_rings; i++, mhi_event++) {  in mhi_deinit_dev_ctxt()
253 		dma_free_coherent(mhi_cntrl->cntrl_dev, ring->alloc_size,  in mhi_deinit_dev_ctxt()
259 	dma_free_coherent(mhi_cntrl->cntrl_dev, sizeof(*mhi_ctxt->er_ctxt) *  in mhi_deinit_dev_ctxt()
260 			  mhi_cntrl->total_ev_rings, mhi_ctxt->er_ctxt,  in mhi_deinit_dev_ctxt()
263 	dma_free_coherent(mhi_cntrl->cntrl_dev, sizeof(*mhi_ctxt->chan_ctxt) *  in mhi_deinit_dev_ctxt()
264 			  mhi_cntrl->max_chan, mhi_ctxt->chan_ctxt,  in mhi_deinit_dev_ctxt()
268 	mhi_cntrl->mhi_ctxt = NULL;  in mhi_deinit_dev_ctxt()
271 int mhi_init_dev_ctxt(struct mhi_controller *mhi_cntrl)  in mhi_init_dev_ctxt()  argument
283 	atomic_set(&mhi_cntrl->dev_wake, 0);  in mhi_init_dev_ctxt()
284 	atomic_set(&mhi_cntrl->pending_pkts, 0);  in mhi_init_dev_ctxt()
291 	mhi_ctxt->chan_ctxt = dma_alloc_coherent(mhi_cntrl->cntrl_dev,  in mhi_init_dev_ctxt()
293 						 mhi_cntrl->max_chan,  in mhi_init_dev_ctxt()
299 	mhi_chan = mhi_cntrl->mhi_chan;  in mhi_init_dev_ctxt()
301 	for (i = 0; i < mhi_cntrl->max_chan; i++, chan_ctxt++, mhi_chan++) {  in mhi_init_dev_ctxt()
323 	mhi_ctxt->er_ctxt = dma_alloc_coherent(mhi_cntrl->cntrl_dev,  in mhi_init_dev_ctxt()
325 					       mhi_cntrl->total_ev_rings,  in mhi_init_dev_ctxt()
332 	mhi_event = mhi_cntrl->mhi_event;  in mhi_init_dev_ctxt()
333 	for (i = 0; i < mhi_cntrl->total_ev_rings; i++, er_ctxt++,  in mhi_init_dev_ctxt()
353 		ret = mhi_alloc_aligned_ring(mhi_cntrl, ring, ring->len);  in mhi_init_dev_ctxt()
370 	mhi_ctxt->cmd_ctxt = dma_alloc_coherent(mhi_cntrl->cntrl_dev,  in mhi_init_dev_ctxt()
378 	mhi_cmd = mhi_cntrl->mhi_cmd;  in mhi_init_dev_ctxt()
386 		ret = mhi_alloc_aligned_ring(mhi_cntrl, ring, ring->len);  in mhi_init_dev_ctxt()
397 	mhi_cntrl->mhi_ctxt = mhi_ctxt;  in mhi_init_dev_ctxt()
405 		dma_free_coherent(mhi_cntrl->cntrl_dev, ring->alloc_size,  in mhi_init_dev_ctxt()
408 	dma_free_coherent(mhi_cntrl->cntrl_dev,  in mhi_init_dev_ctxt()
411 	i = mhi_cntrl->total_ev_rings;  in mhi_init_dev_ctxt()
412 	mhi_event = mhi_cntrl->mhi_event + i;  in mhi_init_dev_ctxt()
421 		dma_free_coherent(mhi_cntrl->cntrl_dev, ring->alloc_size,  in mhi_init_dev_ctxt()
424 	dma_free_coherent(mhi_cntrl->cntrl_dev, sizeof(*mhi_ctxt->er_ctxt) *  in mhi_init_dev_ctxt()
425 			  mhi_cntrl->total_ev_rings, mhi_ctxt->er_ctxt,  in mhi_init_dev_ctxt()
429 	dma_free_coherent(mhi_cntrl->cntrl_dev, sizeof(*mhi_ctxt->chan_ctxt) *  in mhi_init_dev_ctxt()
430 			  mhi_cntrl->max_chan, mhi_ctxt->chan_ctxt,  in mhi_init_dev_ctxt()
439 int mhi_init_mmio(struct mhi_controller *mhi_cntrl)  in mhi_init_mmio()  argument
445 	void __iomem *base = mhi_cntrl->regs;  in mhi_init_mmio()
446 	struct device *dev = &mhi_cntrl->mhi_dev->dev;  in mhi_init_mmio()
453 			upper_32_bits(mhi_cntrl->mhi_ctxt->chan_ctxt_addr),  in mhi_init_mmio()
457 			lower_32_bits(mhi_cntrl->mhi_ctxt->chan_ctxt_addr),  in mhi_init_mmio()
461 			upper_32_bits(mhi_cntrl->mhi_ctxt->er_ctxt_addr),  in mhi_init_mmio()
465 			lower_32_bits(mhi_cntrl->mhi_ctxt->er_ctxt_addr),  in mhi_init_mmio()
469 			upper_32_bits(mhi_cntrl->mhi_ctxt->cmd_ctxt_addr),  in mhi_init_mmio()
473 			lower_32_bits(mhi_cntrl->mhi_ctxt->cmd_ctxt_addr),  in mhi_init_mmio()
477 			upper_32_bits(mhi_cntrl->iova_start),  in mhi_init_mmio()
481 			lower_32_bits(mhi_cntrl->iova_start),  in mhi_init_mmio()
485 			upper_32_bits(mhi_cntrl->iova_start),  in mhi_init_mmio()
489 			lower_32_bits(mhi_cntrl->iova_start),  in mhi_init_mmio()
493 			upper_32_bits(mhi_cntrl->iova_stop),  in mhi_init_mmio()
497 			lower_32_bits(mhi_cntrl->iova_stop),  in mhi_init_mmio()
501 			upper_32_bits(mhi_cntrl->iova_stop),  in mhi_init_mmio()
505 			lower_32_bits(mhi_cntrl->iova_stop),  in mhi_init_mmio()
513 	ret = mhi_read_reg(mhi_cntrl, base, CHDBOFF, &val);  in mhi_init_mmio()
520 	mhi_cntrl->wake_db = base + val + (8 * MHI_DEV_WAKE_DB);  in mhi_init_mmio()
521 	mhi_cntrl->wake_set = false;  in mhi_init_mmio()
524 	mhi_chan = mhi_cntrl->mhi_chan;  in mhi_init_mmio()
525 	for (i = 0; i < mhi_cntrl->max_chan; i++, val += 8, mhi_chan++)  in mhi_init_mmio()
529 	ret = mhi_read_reg(mhi_cntrl, base, ERDBOFF, &val);  in mhi_init_mmio()
536 	mhi_event = mhi_cntrl->mhi_event;  in mhi_init_mmio()
537 	for (i = 0; i < mhi_cntrl->total_ev_rings; i++, val += 8, mhi_event++) {  in mhi_init_mmio()
545 	mhi_cntrl->mhi_cmd[PRIMARY_CMD_RING].ring.db_addr = base + CRDB_LOWER;  in mhi_init_mmio()
549 		mhi_write_reg(mhi_cntrl, base, reg_info[i].offset,  in mhi_init_mmio()
552 	ret = mhi_write_reg_field(mhi_cntrl, base, MHICFG, MHICFG_NER_MASK,  in mhi_init_mmio()
553 				  mhi_cntrl->total_ev_rings);  in mhi_init_mmio()
559 	ret = mhi_write_reg_field(mhi_cntrl, base, MHICFG, MHICFG_NHWER_MASK,  in mhi_init_mmio()
560 				  mhi_cntrl->hw_ev_rings);  in mhi_init_mmio()
569 void mhi_deinit_chan_ctxt(struct mhi_controller *mhi_cntrl,  in mhi_deinit_chan_ctxt()  argument
579 	chan_ctxt = &mhi_cntrl->mhi_ctxt->chan_ctxt[mhi_chan->chan];  in mhi_deinit_chan_ctxt()
584 	dma_free_coherent(mhi_cntrl->cntrl_dev, tre_ring->alloc_size,  in mhi_deinit_chan_ctxt()
604 int mhi_init_chan_ctxt(struct mhi_controller *mhi_cntrl,  in mhi_init_chan_ctxt()  argument
617 	chan_ctxt = &mhi_cntrl->mhi_ctxt->chan_ctxt[mhi_chan->chan];  in mhi_init_chan_ctxt()
618 	ret = mhi_alloc_aligned_ring(mhi_cntrl, tre_ring, tre_ring->len);  in mhi_init_chan_ctxt()
627 		dma_free_coherent(mhi_cntrl->cntrl_dev, tre_ring->alloc_size,  in mhi_init_chan_ctxt()
652 static int parse_ev_cfg(struct mhi_controller *mhi_cntrl,  in parse_ev_cfg()  argument
657 	struct device *dev = mhi_cntrl->cntrl_dev;  in parse_ev_cfg()
661 	mhi_cntrl->total_ev_rings = num;  in parse_ev_cfg()
662 	mhi_cntrl->mhi_event = kcalloc(num, sizeof(*mhi_cntrl->mhi_event),  in parse_ev_cfg()
664 	if (!mhi_cntrl->mhi_event)  in parse_ev_cfg()
668 	mhi_event = mhi_cntrl->mhi_event;  in parse_ev_cfg()
680 			if (mhi_event->chan >= mhi_cntrl->max_chan) {  in parse_ev_cfg()
687 				&mhi_cntrl->mhi_chan[mhi_event->chan];  in parse_ev_cfg()
718 			mhi_cntrl->hw_ev_rings++;  in parse_ev_cfg()
720 			mhi_cntrl->sw_ev_rings++;  in parse_ev_cfg()
731 	kfree(mhi_cntrl->mhi_event);  in parse_ev_cfg()
735 static int parse_ch_cfg(struct mhi_controller *mhi_cntrl,  in parse_ch_cfg()  argument
739 	struct device *dev = mhi_cntrl->cntrl_dev;  in parse_ch_cfg()
743 	mhi_cntrl->max_chan = config->max_channels;  in parse_ch_cfg()
750 	mhi_cntrl->mhi_chan = vzalloc(mhi_cntrl->max_chan *  in parse_ch_cfg()
751 				      sizeof(*mhi_cntrl->mhi_chan));  in parse_ch_cfg()
752 	if (!mhi_cntrl->mhi_chan)  in parse_ch_cfg()
755 	INIT_LIST_HEAD(&mhi_cntrl->lpm_chans);  in parse_ch_cfg()
764 		if (chan >= mhi_cntrl->max_chan) {  in parse_ch_cfg()
769 		mhi_chan = &mhi_cntrl->mhi_chan[chan];  in parse_ch_cfg()
842 			list_add_tail(&mhi_chan->node, &mhi_cntrl->lpm_chans);  in parse_ch_cfg()
848 	vfree(mhi_cntrl->mhi_chan);  in parse_ch_cfg()
853 static int parse_config(struct mhi_controller *mhi_cntrl,  in parse_config()  argument
859 	ret = parse_ch_cfg(mhi_cntrl, config);  in parse_config()
864 	ret = parse_ev_cfg(mhi_cntrl, config);  in parse_config()
868 	mhi_cntrl->timeout_ms = config->timeout_ms;  in parse_config()
869 	if (!mhi_cntrl->timeout_ms)  in parse_config()
870 		mhi_cntrl->timeout_ms = MHI_TIMEOUT_MS;  in parse_config()
872 	mhi_cntrl->bounce_buf = config->use_bounce_buf;  in parse_config()
873 	mhi_cntrl->buffer_len = config->buf_len;  in parse_config()
874 	if (!mhi_cntrl->buffer_len)  in parse_config()
875 		mhi_cntrl->buffer_len = MHI_MAX_MTU;  in parse_config()
878 	mhi_cntrl->db_access = MHI_PM_M0 | MHI_PM_M2;  in parse_config()
880 		mhi_cntrl->db_access &= ~MHI_PM_M2;  in parse_config()
885 	vfree(mhi_cntrl->mhi_chan);  in parse_config()
890 int mhi_register_controller(struct mhi_controller *mhi_cntrl,  in mhi_register_controller()  argument
900 	if (!mhi_cntrl || !mhi_cntrl->cntrl_dev || !mhi_cntrl->regs ||  in mhi_register_controller()
901 	    !mhi_cntrl->runtime_get || !mhi_cntrl->runtime_put ||  in mhi_register_controller()
902 	    !mhi_cntrl->status_cb || !mhi_cntrl->read_reg ||  in mhi_register_controller()
903 	    !mhi_cntrl->write_reg || !mhi_cntrl->nr_irqs ||  in mhi_register_controller()
904 	    !mhi_cntrl->irq || !mhi_cntrl->reg_len)  in mhi_register_controller()
907 	ret = parse_config(mhi_cntrl, config);  in mhi_register_controller()
911 	mhi_cntrl->mhi_cmd = kcalloc(NR_OF_CMD_RINGS,  in mhi_register_controller()
912 				     sizeof(*mhi_cntrl->mhi_cmd), GFP_KERNEL);  in mhi_register_controller()
913 	if (!mhi_cntrl->mhi_cmd) {  in mhi_register_controller()
918 	INIT_LIST_HEAD(&mhi_cntrl->transition_list);  in mhi_register_controller()
919 	mutex_init(&mhi_cntrl->pm_mutex);  in mhi_register_controller()
920 	rwlock_init(&mhi_cntrl->pm_lock);  in mhi_register_controller()
921 	spin_lock_init(&mhi_cntrl->transition_lock);  in mhi_register_controller()
922 	spin_lock_init(&mhi_cntrl->wlock);  in mhi_register_controller()
923 	INIT_WORK(&mhi_cntrl->st_worker, mhi_pm_st_worker);  in mhi_register_controller()
924 	init_waitqueue_head(&mhi_cntrl->state_event);  in mhi_register_controller()
926 	mhi_cntrl->hiprio_wq = alloc_ordered_workqueue("mhi_hiprio_wq", WQ_HIGHPRI);  in mhi_register_controller()
927 	if (!mhi_cntrl->hiprio_wq) {  in mhi_register_controller()
928 		dev_err(mhi_cntrl->cntrl_dev, "Failed to allocate workqueue\n");  in mhi_register_controller()
933 	mhi_cmd = mhi_cntrl->mhi_cmd;  in mhi_register_controller()
937 	mhi_event = mhi_cntrl->mhi_event;  in mhi_register_controller()
938 	for (i = 0; i < mhi_cntrl->total_ev_rings; i++, mhi_event++) {  in mhi_register_controller()
943 		mhi_event->mhi_cntrl = mhi_cntrl;  in mhi_register_controller()
953 	mhi_chan = mhi_cntrl->mhi_chan;  in mhi_register_controller()
954 	for (i = 0; i < mhi_cntrl->max_chan; i++, mhi_chan++) {  in mhi_register_controller()
960 		mhi_event = &mhi_cntrl->mhi_event[mhi_chan->er_index];  in mhi_register_controller()
964 	if (mhi_cntrl->bounce_buf) {  in mhi_register_controller()
965 		mhi_cntrl->map_single = mhi_map_single_use_bb;  in mhi_register_controller()
966 		mhi_cntrl->unmap_single = mhi_unmap_single_use_bb;  in mhi_register_controller()
968 		mhi_cntrl->map_single = mhi_map_single_no_bb;  in mhi_register_controller()
969 		mhi_cntrl->unmap_single = mhi_unmap_single_no_bb;  in mhi_register_controller()
973 	ret = mhi_read_reg(mhi_cntrl, mhi_cntrl->regs,  in mhi_register_controller()
978 	mhi_cntrl->family_number = FIELD_GET(SOC_HW_VERSION_FAM_NUM_BMSK, soc_info);  in mhi_register_controller()
979 	mhi_cntrl->device_number = FIELD_GET(SOC_HW_VERSION_DEV_NUM_BMSK, soc_info);  in mhi_register_controller()
980 	mhi_cntrl->major_version = FIELD_GET(SOC_HW_VERSION_MAJOR_VER_BMSK, soc_info);  in mhi_register_controller()
981 	mhi_cntrl->minor_version = FIELD_GET(SOC_HW_VERSION_MINOR_VER_BMSK, soc_info);  in mhi_register_controller()
983 	mhi_cntrl->index = ida_alloc(&mhi_controller_ida, GFP_KERNEL);  in mhi_register_controller()
984 	if (mhi_cntrl->index < 0) {  in mhi_register_controller()
985 		ret = mhi_cntrl->index;  in mhi_register_controller()
989 	ret = mhi_init_irq_setup(mhi_cntrl);  in mhi_register_controller()
994 	mhi_dev = mhi_alloc_device(mhi_cntrl);  in mhi_register_controller()
996 		dev_err(mhi_cntrl->cntrl_dev, "Failed to allocate MHI device\n");  in mhi_register_controller()
1002 	mhi_dev->mhi_cntrl = mhi_cntrl;  in mhi_register_controller()
1003 	dev_set_name(&mhi_dev->dev, "mhi%d", mhi_cntrl->index);  in mhi_register_controller()
1013 	mhi_cntrl->mhi_dev = mhi_dev;  in mhi_register_controller()
1015 	mhi_create_debugfs(mhi_cntrl);  in mhi_register_controller()
1022 	mhi_deinit_free_irq(mhi_cntrl);  in mhi_register_controller()
1024 	ida_free(&mhi_controller_ida, mhi_cntrl->index);  in mhi_register_controller()
1026 	destroy_workqueue(mhi_cntrl->hiprio_wq);  in mhi_register_controller()
1028 	kfree(mhi_cntrl->mhi_cmd);  in mhi_register_controller()
1030 	kfree(mhi_cntrl->mhi_event);  in mhi_register_controller()
1031 	vfree(mhi_cntrl->mhi_chan);  in mhi_register_controller()
1037 void mhi_unregister_controller(struct mhi_controller *mhi_cntrl)  in mhi_unregister_controller()  argument
1039 	struct mhi_device *mhi_dev = mhi_cntrl->mhi_dev;  in mhi_unregister_controller()
1040 	struct mhi_chan *mhi_chan = mhi_cntrl->mhi_chan;  in mhi_unregister_controller()
1043 	mhi_deinit_free_irq(mhi_cntrl);  in mhi_unregister_controller()
1044 	mhi_destroy_debugfs(mhi_cntrl);  in mhi_unregister_controller()
1046 	destroy_workqueue(mhi_cntrl->hiprio_wq);  in mhi_unregister_controller()
1047 	kfree(mhi_cntrl->mhi_cmd);  in mhi_unregister_controller()
1048 	kfree(mhi_cntrl->mhi_event);  in mhi_unregister_controller()
1051 	for (i = 0; i < mhi_cntrl->max_chan; i++, mhi_chan++) {  in mhi_unregister_controller()
1057 	vfree(mhi_cntrl->mhi_chan);  in mhi_unregister_controller()
1062 	ida_free(&mhi_controller_ida, mhi_cntrl->index);  in mhi_unregister_controller()
1068 	struct mhi_controller *mhi_cntrl;  in mhi_alloc_controller()  local
1070 	mhi_cntrl = kzalloc(sizeof(*mhi_cntrl), GFP_KERNEL);  in mhi_alloc_controller()
1072 	return mhi_cntrl;  in mhi_alloc_controller()
1076 void mhi_free_controller(struct mhi_controller *mhi_cntrl)  in mhi_free_controller()  argument
1078 	kfree(mhi_cntrl);  in mhi_free_controller()
1082 int mhi_prepare_for_power_up(struct mhi_controller *mhi_cntrl)  in mhi_prepare_for_power_up()  argument
1084 	struct device *dev = &mhi_cntrl->mhi_dev->dev;  in mhi_prepare_for_power_up()
1088 	mutex_lock(&mhi_cntrl->pm_mutex);  in mhi_prepare_for_power_up()
1090 	ret = mhi_init_dev_ctxt(mhi_cntrl);  in mhi_prepare_for_power_up()
1094 	ret = mhi_read_reg(mhi_cntrl, mhi_cntrl->regs, BHIOFF, &bhi_off);  in mhi_prepare_for_power_up()
1100 	if (bhi_off >= mhi_cntrl->reg_len) {  in mhi_prepare_for_power_up()
1102 			bhi_off, mhi_cntrl->reg_len);  in mhi_prepare_for_power_up()
1106 	mhi_cntrl->bhi = mhi_cntrl->regs + bhi_off;  in mhi_prepare_for_power_up()
1108 	if (mhi_cntrl->fbc_download || mhi_cntrl->rddm_size) {  in mhi_prepare_for_power_up()
1109 		ret = mhi_read_reg(mhi_cntrl, mhi_cntrl->regs, BHIEOFF,  in mhi_prepare_for_power_up()
1116 		if (bhie_off >= mhi_cntrl->reg_len) {  in mhi_prepare_for_power_up()
1119 				bhie_off, mhi_cntrl->reg_len);  in mhi_prepare_for_power_up()
1123 		mhi_cntrl->bhie = mhi_cntrl->regs + bhie_off;  in mhi_prepare_for_power_up()
1126 	if (mhi_cntrl->rddm_size) {  in mhi_prepare_for_power_up()
1131 		memset_io(mhi_cntrl->bhie + BHIE_RXVECADDR_LOW_OFFS,  in mhi_prepare_for_power_up()
1137 		mhi_alloc_bhie_table(mhi_cntrl, &mhi_cntrl->rddm_image,  in mhi_prepare_for_power_up()
1138 				     mhi_cntrl->rddm_size);  in mhi_prepare_for_power_up()
1139 		if (mhi_cntrl->rddm_image) {  in mhi_prepare_for_power_up()
1140 			ret = mhi_rddm_prepare(mhi_cntrl,  in mhi_prepare_for_power_up()
1141 					       mhi_cntrl->rddm_image);  in mhi_prepare_for_power_up()
1143 				mhi_free_bhie_table(mhi_cntrl,  in mhi_prepare_for_power_up()
1144 						    mhi_cntrl->rddm_image);  in mhi_prepare_for_power_up()
1150 	mutex_unlock(&mhi_cntrl->pm_mutex);  in mhi_prepare_for_power_up()
1155 	mhi_deinit_dev_ctxt(mhi_cntrl);  in mhi_prepare_for_power_up()
1158 	mutex_unlock(&mhi_cntrl->pm_mutex);  in mhi_prepare_for_power_up()
1164 void mhi_unprepare_after_power_down(struct mhi_controller *mhi_cntrl)  in mhi_unprepare_after_power_down()  argument
1166 	if (mhi_cntrl->fbc_image) {  in mhi_unprepare_after_power_down()
1167 		mhi_free_bhie_table(mhi_cntrl, mhi_cntrl->fbc_image);  in mhi_unprepare_after_power_down()
1168 		mhi_cntrl->fbc_image = NULL;  in mhi_unprepare_after_power_down()
1171 	if (mhi_cntrl->rddm_image) {  in mhi_unprepare_after_power_down()
1172 		mhi_free_bhie_table(mhi_cntrl, mhi_cntrl->rddm_image);  in mhi_unprepare_after_power_down()
1173 		mhi_cntrl->rddm_image = NULL;  in mhi_unprepare_after_power_down()
1176 	mhi_cntrl->bhi = NULL;  in mhi_unprepare_after_power_down()
1177 	mhi_cntrl->bhie = NULL;  in mhi_unprepare_after_power_down()
1179 	mhi_deinit_dev_ctxt(mhi_cntrl);  in mhi_unprepare_after_power_down()
1202 struct mhi_device *mhi_alloc_device(struct mhi_controller *mhi_cntrl)  in mhi_alloc_device()  argument
1216 	if (mhi_cntrl->mhi_dev) {  in mhi_alloc_device()
1218 		dev->parent = &mhi_cntrl->mhi_dev->dev;  in mhi_alloc_device()
1221 		dev->parent = mhi_cntrl->cntrl_dev;  in mhi_alloc_device()
1224 	mhi_dev->mhi_cntrl = mhi_cntrl;  in mhi_alloc_device()
1233 	struct mhi_controller *mhi_cntrl = mhi_dev->mhi_cntrl;  in mhi_driver_probe()  local
1276 		mhi_event = &mhi_cntrl->mhi_event[dl_chan->er_index];  in mhi_driver_probe()
1310 	struct mhi_controller *mhi_cntrl = mhi_dev->mhi_cntrl;  in mhi_driver_remove()  local
1344 			mhi_reset_chan(mhi_cntrl, mhi_chan);  in mhi_driver_remove()
1363 			mhi_deinit_chan_ctxt(mhi_cntrl, mhi_chan);  in mhi_driver_remove()