45 static int  cont_map[2] = { 0x08, 0x10 };
76 {       int     h, l, k, ph;  in frpw_read_block_int()  local
81                 for (k=0;k<count;k++) {  in frpw_read_block_int()
84                         buf[k] = j44(l,h);  in frpw_read_block_int()
89         case 1: ph = 2;  in frpw_read_block_int()
92                 for (k=0;k<count;k++) {  in frpw_read_block_int()
94                         buf[k] = r0();  in frpw_read_block_int()
95                         ph = 2 - ph;  in frpw_read_block_int()
100         case 2: w2(4); w0(regr + 0x80); cec4;  in frpw_read_block_int()
101                 for (k=0;k<count;k++) buf[k] = r4();  in frpw_read_block_int()
107 		for (k=0;k<count-2;k++) buf[k] = r4();  in frpw_read_block_int()
109 		buf[count-2] = r4();  in frpw_read_block_int()
115                 for (k=0;k<(count/2)-1;k++) ((u16 *)buf)[k] = r4w();  in frpw_read_block_int()
117                 buf[count-2] = r4();  in frpw_read_block_int()
123                 for (k=0;k<(count/4)-1;k++) ((u32 *)buf)[k] = r4l();  in frpw_read_block_int()
127                 buf[count-2] = r4();  in frpw_read_block_int()
142 {	int	k;  in frpw_write_block()  local
148 	case 2: w2(4); w0(8); cec4; w2(5);  in frpw_write_block()
149         	for (k=0;k<count;k++) {  in frpw_write_block()
150 			w0(buf[k]);  in frpw_write_block()
157 		for (k=0;k<count;k++) w4(buf[k]);  in frpw_write_block()
162                 for (k=0;k<count/2;k++) w4w(((u16 *)buf)[k]);  in frpw_write_block()
167                 for (k=0;k<count/4;k++) w4l(((u32 *)buf)[k]);  in frpw_write_block()
220    To make this work, private = port*2 + chip.  Yes, I know it's
226 {       int     j, k, r;  in frpw_test_proto()  local
227 	int	e[2] = {0,0};  in frpw_test_proto()
230 	   pi->private = frpw_test_pnp(pi) + 2*pi->port;  in frpw_test_proto()
232 	if (((pi->private%2) == 0) && (pi->mode > 2)) {  in frpw_test_proto()
239 	if (((pi->private%2) == 1) && (pi->mode == 2)) {  in frpw_test_proto()
241 		printk("%s: frpw: ASIC does not support mode 2\n",  in frpw_test_proto()
247 	for (j=0;j<2;j++) {  in frpw_test_proto()
249                 for (k=0;k<256;k++) {  in frpw_test_proto()
250                         frpw_write_regr(pi,0,2,k^0xaa);  in frpw_test_proto()
251                         frpw_write_regr(pi,0,3,k^0x55);  in frpw_test_proto()
252                         if (frpw_read_regr(pi,0,2) != (k^0xaa)) e[j]++;  in frpw_test_proto()
260         for (k=0;k<128;k++) if (scratch[k] != k) r++;  in frpw_test_proto()
265                    pi->device,pi->port,(pi->private%2),pi->mode,e[0],e[1],r);  in frpw_test_proto()
278 		FRPW_VERSION,((pi->private%2) == 0)?"Xilinx":"ASIC",pi->port);  in frpw_log_adapter()
288 	.epp_first	= 2,
289 	.default_delay	= 2,