Lines Matching +full:on +full:- +full:chip
1 // SPDX-License-Identifier: GPL-2.0
25 const struct regmap_irq_chip *chip; member
59 return &data->chip->irqs[irq]; in irq_to_regmap_irq()
64 struct regmap *map = data->map; in regmap_irq_can_bulk_read_status()
67 * While possible that a user-defined ->get_irq_reg() callback might in regmap_irq_can_bulk_read_status()
71 return data->irq_reg_stride == 1 && map->reg_stride == 1 && in regmap_irq_can_bulk_read_status()
72 data->get_irq_reg == regmap_irq_get_irq_reg_linear && in regmap_irq_can_bulk_read_status()
73 !map->use_single_read; in regmap_irq_can_bulk_read_status()
80 mutex_lock(&d->lock); in regmap_irq_lock()
86 struct regmap *map = d->map; in regmap_irq_sync_unlock()
91 if (d->chip->runtime_pm) { in regmap_irq_sync_unlock()
92 ret = pm_runtime_get_sync(map->dev); in regmap_irq_sync_unlock()
94 dev_err(map->dev, "IRQ sync failed to resume: %d\n", in regmap_irq_sync_unlock()
98 if (d->clear_status) { in regmap_irq_sync_unlock()
99 for (i = 0; i < d->chip->num_regs; i++) { in regmap_irq_sync_unlock()
100 reg = d->get_irq_reg(d, d->chip->status_base, i); in regmap_irq_sync_unlock()
104 dev_err(d->map->dev, in regmap_irq_sync_unlock()
108 d->clear_status = false; in regmap_irq_sync_unlock()
113 * hardware. We rely on the use of the regmap core cache to in regmap_irq_sync_unlock()
116 for (i = 0; i < d->chip->num_regs; i++) { in regmap_irq_sync_unlock()
117 if (d->mask_base) { in regmap_irq_sync_unlock()
118 reg = d->get_irq_reg(d, d->mask_base, i); in regmap_irq_sync_unlock()
119 ret = regmap_update_bits(d->map, reg, in regmap_irq_sync_unlock()
120 d->mask_buf_def[i], d->mask_buf[i]); in regmap_irq_sync_unlock()
122 dev_err(d->map->dev, "Failed to sync masks in %x\n", in regmap_irq_sync_unlock()
126 if (d->unmask_base) { in regmap_irq_sync_unlock()
127 reg = d->get_irq_reg(d, d->unmask_base, i); in regmap_irq_sync_unlock()
128 ret = regmap_update_bits(d->map, reg, in regmap_irq_sync_unlock()
129 d->mask_buf_def[i], ~d->mask_buf[i]); in regmap_irq_sync_unlock()
131 dev_err(d->map->dev, "Failed to sync masks in %x\n", in regmap_irq_sync_unlock()
135 reg = d->get_irq_reg(d, d->chip->wake_base, i); in regmap_irq_sync_unlock()
136 if (d->wake_buf) { in regmap_irq_sync_unlock()
137 if (d->chip->wake_invert) in regmap_irq_sync_unlock()
138 ret = regmap_update_bits(d->map, reg, in regmap_irq_sync_unlock()
139 d->mask_buf_def[i], in regmap_irq_sync_unlock()
140 ~d->wake_buf[i]); in regmap_irq_sync_unlock()
142 ret = regmap_update_bits(d->map, reg, in regmap_irq_sync_unlock()
143 d->mask_buf_def[i], in regmap_irq_sync_unlock()
144 d->wake_buf[i]); in regmap_irq_sync_unlock()
146 dev_err(d->map->dev, in regmap_irq_sync_unlock()
151 if (!d->chip->init_ack_masked) in regmap_irq_sync_unlock()
158 if (d->mask_buf[i] && (d->chip->ack_base || d->chip->use_ack)) { in regmap_irq_sync_unlock()
159 reg = d->get_irq_reg(d, d->chip->ack_base, i); in regmap_irq_sync_unlock()
162 if (d->chip->ack_invert) in regmap_irq_sync_unlock()
163 ret = regmap_write(map, reg, ~d->mask_buf[i]); in regmap_irq_sync_unlock()
165 ret = regmap_write(map, reg, d->mask_buf[i]); in regmap_irq_sync_unlock()
166 if (d->chip->clear_ack) { in regmap_irq_sync_unlock()
167 if (d->chip->ack_invert && !ret) in regmap_irq_sync_unlock()
173 dev_err(d->map->dev, "Failed to ack 0x%x: %d\n", in regmap_irq_sync_unlock()
179 if (!d->chip->type_in_mask) { in regmap_irq_sync_unlock()
180 for (i = 0; i < d->chip->num_type_reg; i++) { in regmap_irq_sync_unlock()
181 if (!d->type_buf_def[i]) in regmap_irq_sync_unlock()
183 reg = d->get_irq_reg(d, d->chip->type_base, i); in regmap_irq_sync_unlock()
184 if (d->chip->type_invert) in regmap_irq_sync_unlock()
185 ret = regmap_update_bits(d->map, reg, in regmap_irq_sync_unlock()
186 d->type_buf_def[i], ~d->type_buf[i]); in regmap_irq_sync_unlock()
188 ret = regmap_update_bits(d->map, reg, in regmap_irq_sync_unlock()
189 d->type_buf_def[i], d->type_buf[i]); in regmap_irq_sync_unlock()
191 dev_err(d->map->dev, "Failed to sync type in %x\n", in regmap_irq_sync_unlock()
196 if (d->chip->num_virt_regs) { in regmap_irq_sync_unlock()
197 for (i = 0; i < d->chip->num_virt_regs; i++) { in regmap_irq_sync_unlock()
198 for (j = 0; j < d->chip->num_regs; j++) { in regmap_irq_sync_unlock()
199 reg = d->get_irq_reg(d, d->chip->virt_reg_base[i], in regmap_irq_sync_unlock()
201 ret = regmap_write(map, reg, d->virt_buf[i][j]); in regmap_irq_sync_unlock()
203 dev_err(d->map->dev, in regmap_irq_sync_unlock()
210 for (i = 0; i < d->chip->num_config_bases; i++) { in regmap_irq_sync_unlock()
211 for (j = 0; j < d->chip->num_config_regs; j++) { in regmap_irq_sync_unlock()
212 reg = d->get_irq_reg(d, d->chip->config_base[i], j); in regmap_irq_sync_unlock()
213 ret = regmap_write(map, reg, d->config_buf[i][j]); in regmap_irq_sync_unlock()
215 dev_err(d->map->dev, in regmap_irq_sync_unlock()
221 if (d->chip->runtime_pm) in regmap_irq_sync_unlock()
222 pm_runtime_put(map->dev); in regmap_irq_sync_unlock()
225 if (d->wake_count < 0) in regmap_irq_sync_unlock()
226 for (i = d->wake_count; i < 0; i++) in regmap_irq_sync_unlock()
227 irq_set_irq_wake(d->irq, 0); in regmap_irq_sync_unlock()
228 else if (d->wake_count > 0) in regmap_irq_sync_unlock()
229 for (i = 0; i < d->wake_count; i++) in regmap_irq_sync_unlock()
230 irq_set_irq_wake(d->irq, 1); in regmap_irq_sync_unlock()
232 d->wake_count = 0; in regmap_irq_sync_unlock()
234 mutex_unlock(&d->lock); in regmap_irq_sync_unlock()
240 struct regmap *map = d->map; in regmap_irq_enable()
241 const struct regmap_irq *irq_data = irq_to_regmap_irq(d, data->hwirq); in regmap_irq_enable()
242 unsigned int reg = irq_data->reg_offset / map->reg_stride; in regmap_irq_enable()
255 if (d->chip->type_in_mask && irq_data->type.types_supported) in regmap_irq_enable()
256 mask = d->type_buf[reg] & irq_data->mask; in regmap_irq_enable()
258 mask = irq_data->mask; in regmap_irq_enable()
260 if (d->chip->clear_on_unmask) in regmap_irq_enable()
261 d->clear_status = true; in regmap_irq_enable()
263 d->mask_buf[reg] &= ~mask; in regmap_irq_enable()
269 struct regmap *map = d->map; in regmap_irq_disable()
270 const struct regmap_irq *irq_data = irq_to_regmap_irq(d, data->hwirq); in regmap_irq_disable()
272 d->mask_buf[irq_data->reg_offset / map->reg_stride] |= irq_data->mask; in regmap_irq_disable()
278 struct regmap *map = d->map; in regmap_irq_set_type()
279 const struct regmap_irq *irq_data = irq_to_regmap_irq(d, data->hwirq); in regmap_irq_set_type()
281 const struct regmap_irq_type *t = &irq_data->type; in regmap_irq_set_type()
283 if ((t->types_supported & type) != type) in regmap_irq_set_type()
286 reg = t->type_reg_offset / map->reg_stride; in regmap_irq_set_type()
288 if (t->type_reg_mask) in regmap_irq_set_type()
289 d->type_buf[reg] &= ~t->type_reg_mask; in regmap_irq_set_type()
291 d->type_buf[reg] &= ~(t->type_falling_val | in regmap_irq_set_type()
292 t->type_rising_val | in regmap_irq_set_type()
293 t->type_level_low_val | in regmap_irq_set_type()
294 t->type_level_high_val); in regmap_irq_set_type()
297 d->type_buf[reg] |= t->type_falling_val; in regmap_irq_set_type()
301 d->type_buf[reg] |= t->type_rising_val; in regmap_irq_set_type()
305 d->type_buf[reg] |= (t->type_falling_val | in regmap_irq_set_type()
306 t->type_rising_val); in regmap_irq_set_type()
310 d->type_buf[reg] |= t->type_level_high_val; in regmap_irq_set_type()
314 d->type_buf[reg] |= t->type_level_low_val; in regmap_irq_set_type()
317 return -EINVAL; in regmap_irq_set_type()
320 if (d->chip->set_type_virt) { in regmap_irq_set_type()
321 ret = d->chip->set_type_virt(d->virt_buf, type, data->hwirq, in regmap_irq_set_type()
327 if (d->chip->set_type_config) { in regmap_irq_set_type()
328 ret = d->chip->set_type_config(d->config_buf, type, in regmap_irq_set_type()
337 static int regmap_irq_set_wake(struct irq_data *data, unsigned int on) in regmap_irq_set_wake() argument
340 struct regmap *map = d->map; in regmap_irq_set_wake()
341 const struct regmap_irq *irq_data = irq_to_regmap_irq(d, data->hwirq); in regmap_irq_set_wake()
343 if (on) { in regmap_irq_set_wake()
344 if (d->wake_buf) in regmap_irq_set_wake()
345 d->wake_buf[irq_data->reg_offset / map->reg_stride] in regmap_irq_set_wake()
346 &= ~irq_data->mask; in regmap_irq_set_wake()
347 d->wake_count++; in regmap_irq_set_wake()
349 if (d->wake_buf) in regmap_irq_set_wake()
350 d->wake_buf[irq_data->reg_offset / map->reg_stride] in regmap_irq_set_wake()
351 |= irq_data->mask; in regmap_irq_set_wake()
352 d->wake_count--; in regmap_irq_set_wake()
370 const struct regmap_irq_chip *chip = data->chip; in read_sub_irq_data() local
371 struct regmap *map = data->map; in read_sub_irq_data()
376 if (!chip->sub_reg_offsets) { in read_sub_irq_data()
377 reg = data->get_irq_reg(data, chip->status_base, b); in read_sub_irq_data()
378 ret = regmap_read(map, reg, &data->status_buf[b]); in read_sub_irq_data()
381 * Note we can't use ->get_irq_reg() here because the offsets in read_sub_irq_data()
384 subreg = &chip->sub_reg_offsets[b]; in read_sub_irq_data()
385 for (i = 0; i < subreg->num_regs; i++) { in read_sub_irq_data()
386 unsigned int offset = subreg->offset[i]; in read_sub_irq_data()
387 unsigned int index = offset / map->reg_stride; in read_sub_irq_data()
389 if (chip->not_fixed_stride) in read_sub_irq_data()
391 chip->status_base + offset, in read_sub_irq_data()
392 &data->status_buf[b]); in read_sub_irq_data()
395 chip->status_base + offset, in read_sub_irq_data()
396 &data->status_buf[index]); in read_sub_irq_data()
408 const struct regmap_irq_chip *chip = data->chip; in regmap_irq_thread() local
409 struct regmap *map = data->map; in regmap_irq_thread()
414 if (chip->handle_pre_irq) in regmap_irq_thread()
415 chip->handle_pre_irq(chip->irq_drv_data); in regmap_irq_thread()
417 if (chip->runtime_pm) { in regmap_irq_thread()
418 ret = pm_runtime_get_sync(map->dev); in regmap_irq_thread()
420 dev_err(map->dev, "IRQ thread failed to resume: %d\n", in regmap_irq_thread()
427 * Read only registers with active IRQs if the chip has 'main status in regmap_irq_thread()
432 if (chip->num_main_regs) { in regmap_irq_thread()
436 size = chip->num_regs * sizeof(unsigned int); in regmap_irq_thread()
438 max_main_bits = (chip->num_main_status_bits) ? in regmap_irq_thread()
439 chip->num_main_status_bits : chip->num_regs; in regmap_irq_thread()
441 memset(data->status_buf, 0, size); in regmap_irq_thread()
448 for (i = 0; i < chip->num_main_regs; i++) { in regmap_irq_thread()
450 * For not_fixed_stride, don't use ->get_irq_reg(). in regmap_irq_thread()
453 if (data->chip->not_fixed_stride) in regmap_irq_thread()
454 reg = chip->main_status + in regmap_irq_thread()
455 i * map->reg_stride * data->irq_reg_stride; in regmap_irq_thread()
457 reg = data->get_irq_reg(data, in regmap_irq_thread()
458 chip->main_status, i); in regmap_irq_thread()
460 ret = regmap_read(map, reg, &data->main_status_buf[i]); in regmap_irq_thread()
462 dev_err(map->dev, in regmap_irq_thread()
470 for (i = 0; i < chip->num_main_regs; i++) { in regmap_irq_thread()
472 const unsigned long mreg = data->main_status_buf[i]; in regmap_irq_thread()
474 for_each_set_bit(b, &mreg, map->format.val_bytes * 8) { in regmap_irq_thread()
475 if (i * map->format.val_bytes * 8 + b > in regmap_irq_thread()
481 dev_err(map->dev, in regmap_irq_thread()
491 u8 *buf8 = data->status_reg_buf; in regmap_irq_thread()
492 u16 *buf16 = data->status_reg_buf; in regmap_irq_thread()
493 u32 *buf32 = data->status_reg_buf; in regmap_irq_thread()
495 BUG_ON(!data->status_reg_buf); in regmap_irq_thread()
497 ret = regmap_bulk_read(map, chip->status_base, in regmap_irq_thread()
498 data->status_reg_buf, in regmap_irq_thread()
499 chip->num_regs); in regmap_irq_thread()
501 dev_err(map->dev, "Failed to read IRQ status: %d\n", in regmap_irq_thread()
506 for (i = 0; i < data->chip->num_regs; i++) { in regmap_irq_thread()
507 switch (map->format.val_bytes) { in regmap_irq_thread()
509 data->status_buf[i] = buf8[i]; in regmap_irq_thread()
512 data->status_buf[i] = buf16[i]; in regmap_irq_thread()
515 data->status_buf[i] = buf32[i]; in regmap_irq_thread()
524 for (i = 0; i < data->chip->num_regs; i++) { in regmap_irq_thread()
525 unsigned int reg = data->get_irq_reg(data, in regmap_irq_thread()
526 data->chip->status_base, i); in regmap_irq_thread()
527 ret = regmap_read(map, reg, &data->status_buf[i]); in regmap_irq_thread()
530 dev_err(map->dev, in regmap_irq_thread()
538 if (chip->status_invert) in regmap_irq_thread()
539 for (i = 0; i < data->chip->num_regs; i++) in regmap_irq_thread()
540 data->status_buf[i] = ~data->status_buf[i]; in regmap_irq_thread()
549 for (i = 0; i < data->chip->num_regs; i++) { in regmap_irq_thread()
550 data->status_buf[i] &= ~data->mask_buf[i]; in regmap_irq_thread()
552 if (data->status_buf[i] && (chip->ack_base || chip->use_ack)) { in regmap_irq_thread()
553 reg = data->get_irq_reg(data, data->chip->ack_base, i); in regmap_irq_thread()
555 if (chip->ack_invert) in regmap_irq_thread()
557 ~data->status_buf[i]); in regmap_irq_thread()
560 data->status_buf[i]); in regmap_irq_thread()
561 if (chip->clear_ack) { in regmap_irq_thread()
562 if (chip->ack_invert && !ret) in regmap_irq_thread()
568 dev_err(map->dev, "Failed to ack 0x%x: %d\n", in regmap_irq_thread()
573 for (i = 0; i < chip->num_irqs; i++) { in regmap_irq_thread()
574 if (data->status_buf[chip->irqs[i].reg_offset / in regmap_irq_thread()
575 map->reg_stride] & chip->irqs[i].mask) { in regmap_irq_thread()
576 handle_nested_irq(irq_find_mapping(data->domain, i)); in regmap_irq_thread()
582 if (chip->runtime_pm) in regmap_irq_thread()
583 pm_runtime_put(map->dev); in regmap_irq_thread()
585 if (chip->handle_post_irq) in regmap_irq_thread()
586 chip->handle_post_irq(chip->irq_drv_data); in regmap_irq_thread()
597 struct regmap_irq_chip_data *data = h->host_data; in regmap_irq_map()
600 irq_set_chip(virq, &data->irq_chip); in regmap_irq_map()
602 irq_set_parent(virq, data->irq); in regmap_irq_map()
614 * regmap_irq_get_irq_reg_linear() - Linear IRQ register mapping callback.
625 const struct regmap_irq_chip *chip = data->chip; in regmap_irq_get_irq_reg_linear() local
626 struct regmap *map = data->map; in regmap_irq_get_irq_reg_linear()
630 * when not_fixed_stride is dropped (it's only used by qcom-pm8008). in regmap_irq_get_irq_reg_linear()
632 if (chip->not_fixed_stride && chip->sub_reg_offsets) { in regmap_irq_get_irq_reg_linear()
635 subreg = &chip->sub_reg_offsets[0]; in regmap_irq_get_irq_reg_linear()
636 return base + subreg->offset[0]; in regmap_irq_get_irq_reg_linear()
639 return base + index * map->reg_stride * data->irq_reg_stride; in regmap_irq_get_irq_reg_linear()
644 * regmap_irq_set_type_config_simple() - Simple IRQ type configuration callback.
651 * This is a &struct regmap_irq_chip->set_type_config callback suitable for
658 const struct regmap_irq_type *t = &irq_data->type; in regmap_irq_set_type_config_simple()
660 if (t->type_reg_mask) in regmap_irq_set_type_config_simple()
661 buf[0][idx] &= ~t->type_reg_mask; in regmap_irq_set_type_config_simple()
663 buf[0][idx] &= ~(t->type_falling_val | in regmap_irq_set_type_config_simple()
664 t->type_rising_val | in regmap_irq_set_type_config_simple()
665 t->type_level_low_val | in regmap_irq_set_type_config_simple()
666 t->type_level_high_val); in regmap_irq_set_type_config_simple()
670 buf[0][idx] |= t->type_falling_val; in regmap_irq_set_type_config_simple()
674 buf[0][idx] |= t->type_rising_val; in regmap_irq_set_type_config_simple()
678 buf[0][idx] |= (t->type_falling_val | in regmap_irq_set_type_config_simple()
679 t->type_rising_val); in regmap_irq_set_type_config_simple()
683 buf[0][idx] |= t->type_level_high_val; in regmap_irq_set_type_config_simple()
687 buf[0][idx] |= t->type_level_low_val; in regmap_irq_set_type_config_simple()
691 return -EINVAL; in regmap_irq_set_type_config_simple()
699 * regmap_add_irq_chip_fwnode() - Use standard regmap IRQ controller handling
706 * @chip: Configuration for the interrupt controller.
707 * @data: Runtime data structure for the controller, allocated on success.
709 * Returns 0 on success or an errno on failure.
711 * In order for this to be efficient the chip really should use a
712 * register cache. The chip driver is responsible for restoring the
718 const struct regmap_irq_chip *chip, in regmap_add_irq_chip_fwnode() argument
723 int ret = -ENOMEM; in regmap_add_irq_chip_fwnode()
727 if (chip->num_regs <= 0) in regmap_add_irq_chip_fwnode()
728 return -EINVAL; in regmap_add_irq_chip_fwnode()
730 if (chip->clear_on_unmask && (chip->ack_base || chip->use_ack)) in regmap_add_irq_chip_fwnode()
731 return -EINVAL; in regmap_add_irq_chip_fwnode()
733 for (i = 0; i < chip->num_irqs; i++) { in regmap_add_irq_chip_fwnode()
734 if (chip->irqs[i].reg_offset % map->reg_stride) in regmap_add_irq_chip_fwnode()
735 return -EINVAL; in regmap_add_irq_chip_fwnode()
736 if (chip->irqs[i].reg_offset / map->reg_stride >= in regmap_add_irq_chip_fwnode()
737 chip->num_regs) in regmap_add_irq_chip_fwnode()
738 return -EINVAL; in regmap_add_irq_chip_fwnode()
741 if (chip->not_fixed_stride) { in regmap_add_irq_chip_fwnode()
742 dev_warn(map->dev, "not_fixed_stride is deprecated; use ->get_irq_reg() instead"); in regmap_add_irq_chip_fwnode()
744 for (i = 0; i < chip->num_regs; i++) in regmap_add_irq_chip_fwnode()
745 if (chip->sub_reg_offsets[i].num_regs != 1) in regmap_add_irq_chip_fwnode()
746 return -EINVAL; in regmap_add_irq_chip_fwnode()
749 if (chip->num_type_reg) in regmap_add_irq_chip_fwnode()
750 dev_warn(map->dev, "type registers are deprecated; use config registers instead"); in regmap_add_irq_chip_fwnode()
752 if (chip->num_virt_regs || chip->virt_reg_base || chip->set_type_virt) in regmap_add_irq_chip_fwnode()
753 dev_warn(map->dev, "virtual registers are deprecated; use config registers instead"); in regmap_add_irq_chip_fwnode()
756 irq_base = irq_alloc_descs(irq_base, 0, chip->num_irqs, 0); in regmap_add_irq_chip_fwnode()
758 dev_warn(map->dev, "Failed to allocate IRQs: %d\n", in regmap_add_irq_chip_fwnode()
766 return -ENOMEM; in regmap_add_irq_chip_fwnode()
768 if (chip->num_main_regs) { in regmap_add_irq_chip_fwnode()
769 d->main_status_buf = kcalloc(chip->num_main_regs, in regmap_add_irq_chip_fwnode()
770 sizeof(*d->main_status_buf), in regmap_add_irq_chip_fwnode()
773 if (!d->main_status_buf) in regmap_add_irq_chip_fwnode()
777 d->status_buf = kcalloc(chip->num_regs, sizeof(*d->status_buf), in regmap_add_irq_chip_fwnode()
779 if (!d->status_buf) in regmap_add_irq_chip_fwnode()
782 d->mask_buf = kcalloc(chip->num_regs, sizeof(*d->mask_buf), in regmap_add_irq_chip_fwnode()
784 if (!d->mask_buf) in regmap_add_irq_chip_fwnode()
787 d->mask_buf_def = kcalloc(chip->num_regs, sizeof(*d->mask_buf_def), in regmap_add_irq_chip_fwnode()
789 if (!d->mask_buf_def) in regmap_add_irq_chip_fwnode()
792 if (chip->wake_base) { in regmap_add_irq_chip_fwnode()
793 d->wake_buf = kcalloc(chip->num_regs, sizeof(*d->wake_buf), in regmap_add_irq_chip_fwnode()
795 if (!d->wake_buf) in regmap_add_irq_chip_fwnode()
799 num_type_reg = chip->type_in_mask ? chip->num_regs : chip->num_type_reg; in regmap_add_irq_chip_fwnode()
801 d->type_buf_def = kcalloc(num_type_reg, in regmap_add_irq_chip_fwnode()
802 sizeof(*d->type_buf_def), GFP_KERNEL); in regmap_add_irq_chip_fwnode()
803 if (!d->type_buf_def) in regmap_add_irq_chip_fwnode()
806 d->type_buf = kcalloc(num_type_reg, sizeof(*d->type_buf), in regmap_add_irq_chip_fwnode()
808 if (!d->type_buf) in regmap_add_irq_chip_fwnode()
812 if (chip->num_virt_regs) { in regmap_add_irq_chip_fwnode()
814 * Create virt_buf[chip->num_extra_config_regs][chip->num_regs] in regmap_add_irq_chip_fwnode()
816 d->virt_buf = kcalloc(chip->num_virt_regs, sizeof(*d->virt_buf), in regmap_add_irq_chip_fwnode()
818 if (!d->virt_buf) in regmap_add_irq_chip_fwnode()
821 for (i = 0; i < chip->num_virt_regs; i++) { in regmap_add_irq_chip_fwnode()
822 d->virt_buf[i] = kcalloc(chip->num_regs, in regmap_add_irq_chip_fwnode()
823 sizeof(**d->virt_buf), in regmap_add_irq_chip_fwnode()
825 if (!d->virt_buf[i]) in regmap_add_irq_chip_fwnode()
830 if (chip->num_config_bases && chip->num_config_regs) { in regmap_add_irq_chip_fwnode()
834 d->config_buf = kcalloc(chip->num_config_bases, in regmap_add_irq_chip_fwnode()
835 sizeof(*d->config_buf), GFP_KERNEL); in regmap_add_irq_chip_fwnode()
836 if (!d->config_buf) in regmap_add_irq_chip_fwnode()
839 for (i = 0; i < chip->num_config_regs; i++) { in regmap_add_irq_chip_fwnode()
840 d->config_buf[i] = kcalloc(chip->num_config_regs, in regmap_add_irq_chip_fwnode()
841 sizeof(**d->config_buf), in regmap_add_irq_chip_fwnode()
843 if (!d->config_buf[i]) in regmap_add_irq_chip_fwnode()
848 d->irq_chip = regmap_irq_chip; in regmap_add_irq_chip_fwnode()
849 d->irq_chip.name = chip->name; in regmap_add_irq_chip_fwnode()
850 d->irq = irq; in regmap_add_irq_chip_fwnode()
851 d->map = map; in regmap_add_irq_chip_fwnode()
852 d->chip = chip; in regmap_add_irq_chip_fwnode()
853 d->irq_base = irq_base; in regmap_add_irq_chip_fwnode()
855 if (chip->mask_base && chip->unmask_base && in regmap_add_irq_chip_fwnode()
856 !chip->mask_unmask_non_inverted) { in regmap_add_irq_chip_fwnode()
860 * for the normal, non-inverted behavior. This "inverted by in regmap_add_irq_chip_fwnode()
868 dev_warn(map->dev, "mask_base and unmask_base are inverted, please fix it"); in regmap_add_irq_chip_fwnode()
871 if (chip->mask_invert) in regmap_add_irq_chip_fwnode()
872 dev_warn(map->dev, "mask_invert=true ignored"); in regmap_add_irq_chip_fwnode()
874 d->mask_base = chip->unmask_base; in regmap_add_irq_chip_fwnode()
875 d->unmask_base = chip->mask_base; in regmap_add_irq_chip_fwnode()
876 } else if (chip->mask_invert) { in regmap_add_irq_chip_fwnode()
882 dev_warn(map->dev, "mask_invert=true is deprecated; please switch to unmask_base"); in regmap_add_irq_chip_fwnode()
884 d->mask_base = chip->unmask_base; in regmap_add_irq_chip_fwnode()
885 d->unmask_base = chip->mask_base; in regmap_add_irq_chip_fwnode()
887 d->mask_base = chip->mask_base; in regmap_add_irq_chip_fwnode()
888 d->unmask_base = chip->unmask_base; in regmap_add_irq_chip_fwnode()
891 if (chip->irq_reg_stride) in regmap_add_irq_chip_fwnode()
892 d->irq_reg_stride = chip->irq_reg_stride; in regmap_add_irq_chip_fwnode()
894 d->irq_reg_stride = 1; in regmap_add_irq_chip_fwnode()
896 if (chip->get_irq_reg) in regmap_add_irq_chip_fwnode()
897 d->get_irq_reg = chip->get_irq_reg; in regmap_add_irq_chip_fwnode()
899 d->get_irq_reg = regmap_irq_get_irq_reg_linear; in regmap_add_irq_chip_fwnode()
902 d->status_reg_buf = kmalloc_array(chip->num_regs, in regmap_add_irq_chip_fwnode()
903 map->format.val_bytes, in regmap_add_irq_chip_fwnode()
905 if (!d->status_reg_buf) in regmap_add_irq_chip_fwnode()
909 mutex_init(&d->lock); in regmap_add_irq_chip_fwnode()
911 for (i = 0; i < chip->num_irqs; i++) in regmap_add_irq_chip_fwnode()
912 d->mask_buf_def[chip->irqs[i].reg_offset / map->reg_stride] in regmap_add_irq_chip_fwnode()
913 |= chip->irqs[i].mask; in regmap_add_irq_chip_fwnode()
916 for (i = 0; i < chip->num_regs; i++) { in regmap_add_irq_chip_fwnode()
917 d->mask_buf[i] = d->mask_buf_def[i]; in regmap_add_irq_chip_fwnode()
919 if (d->mask_base) { in regmap_add_irq_chip_fwnode()
920 reg = d->get_irq_reg(d, d->mask_base, i); in regmap_add_irq_chip_fwnode()
921 ret = regmap_update_bits(d->map, reg, in regmap_add_irq_chip_fwnode()
922 d->mask_buf_def[i], d->mask_buf[i]); in regmap_add_irq_chip_fwnode()
924 dev_err(map->dev, "Failed to set masks in 0x%x: %d\n", in regmap_add_irq_chip_fwnode()
930 if (d->unmask_base) { in regmap_add_irq_chip_fwnode()
931 reg = d->get_irq_reg(d, d->unmask_base, i); in regmap_add_irq_chip_fwnode()
932 ret = regmap_update_bits(d->map, reg, in regmap_add_irq_chip_fwnode()
933 d->mask_buf_def[i], ~d->mask_buf[i]); in regmap_add_irq_chip_fwnode()
935 dev_err(map->dev, "Failed to set masks in 0x%x: %d\n", in regmap_add_irq_chip_fwnode()
941 if (!chip->init_ack_masked) in regmap_add_irq_chip_fwnode()
945 reg = d->get_irq_reg(d, d->chip->status_base, i); in regmap_add_irq_chip_fwnode()
946 ret = regmap_read(map, reg, &d->status_buf[i]); in regmap_add_irq_chip_fwnode()
948 dev_err(map->dev, "Failed to read IRQ status: %d\n", in regmap_add_irq_chip_fwnode()
953 if (chip->status_invert) in regmap_add_irq_chip_fwnode()
954 d->status_buf[i] = ~d->status_buf[i]; in regmap_add_irq_chip_fwnode()
956 if (d->status_buf[i] && (chip->ack_base || chip->use_ack)) { in regmap_add_irq_chip_fwnode()
957 reg = d->get_irq_reg(d, d->chip->ack_base, i); in regmap_add_irq_chip_fwnode()
958 if (chip->ack_invert) in regmap_add_irq_chip_fwnode()
960 ~(d->status_buf[i] & d->mask_buf[i])); in regmap_add_irq_chip_fwnode()
963 d->status_buf[i] & d->mask_buf[i]); in regmap_add_irq_chip_fwnode()
964 if (chip->clear_ack) { in regmap_add_irq_chip_fwnode()
965 if (chip->ack_invert && !ret) in regmap_add_irq_chip_fwnode()
971 dev_err(map->dev, "Failed to ack 0x%x: %d\n", in regmap_add_irq_chip_fwnode()
979 if (d->wake_buf) { in regmap_add_irq_chip_fwnode()
980 for (i = 0; i < chip->num_regs; i++) { in regmap_add_irq_chip_fwnode()
981 d->wake_buf[i] = d->mask_buf_def[i]; in regmap_add_irq_chip_fwnode()
982 reg = d->get_irq_reg(d, d->chip->wake_base, i); in regmap_add_irq_chip_fwnode()
984 if (chip->wake_invert) in regmap_add_irq_chip_fwnode()
985 ret = regmap_update_bits(d->map, reg, in regmap_add_irq_chip_fwnode()
986 d->mask_buf_def[i], in regmap_add_irq_chip_fwnode()
989 ret = regmap_update_bits(d->map, reg, in regmap_add_irq_chip_fwnode()
990 d->mask_buf_def[i], in regmap_add_irq_chip_fwnode()
991 d->wake_buf[i]); in regmap_add_irq_chip_fwnode()
993 dev_err(map->dev, "Failed to set masks in 0x%x: %d\n", in regmap_add_irq_chip_fwnode()
1000 if (chip->num_type_reg && !chip->type_in_mask) { in regmap_add_irq_chip_fwnode()
1001 for (i = 0; i < chip->num_type_reg; ++i) { in regmap_add_irq_chip_fwnode()
1002 reg = d->get_irq_reg(d, d->chip->type_base, i); in regmap_add_irq_chip_fwnode()
1004 ret = regmap_read(map, reg, &d->type_buf_def[i]); in regmap_add_irq_chip_fwnode()
1006 if (d->chip->type_invert) in regmap_add_irq_chip_fwnode()
1007 d->type_buf_def[i] = ~d->type_buf_def[i]; in regmap_add_irq_chip_fwnode()
1010 dev_err(map->dev, "Failed to get type defaults at 0x%x: %d\n", in regmap_add_irq_chip_fwnode()
1018 d->domain = irq_domain_create_legacy(fwnode, chip->num_irqs, in regmap_add_irq_chip_fwnode()
1022 d->domain = irq_domain_create_linear(fwnode, chip->num_irqs, in regmap_add_irq_chip_fwnode()
1024 if (!d->domain) { in regmap_add_irq_chip_fwnode()
1025 dev_err(map->dev, "Failed to create IRQ domain\n"); in regmap_add_irq_chip_fwnode()
1026 ret = -ENOMEM; in regmap_add_irq_chip_fwnode()
1032 chip->name, d); in regmap_add_irq_chip_fwnode()
1034 dev_err(map->dev, "Failed to request IRQ %d for %s: %d\n", in regmap_add_irq_chip_fwnode()
1035 irq, chip->name, ret); in regmap_add_irq_chip_fwnode()
1046 kfree(d->type_buf); in regmap_add_irq_chip_fwnode()
1047 kfree(d->type_buf_def); in regmap_add_irq_chip_fwnode()
1048 kfree(d->wake_buf); in regmap_add_irq_chip_fwnode()
1049 kfree(d->mask_buf_def); in regmap_add_irq_chip_fwnode()
1050 kfree(d->mask_buf); in regmap_add_irq_chip_fwnode()
1051 kfree(d->status_buf); in regmap_add_irq_chip_fwnode()
1052 kfree(d->status_reg_buf); in regmap_add_irq_chip_fwnode()
1053 if (d->virt_buf) { in regmap_add_irq_chip_fwnode()
1054 for (i = 0; i < chip->num_virt_regs; i++) in regmap_add_irq_chip_fwnode()
1055 kfree(d->virt_buf[i]); in regmap_add_irq_chip_fwnode()
1056 kfree(d->virt_buf); in regmap_add_irq_chip_fwnode()
1058 if (d->config_buf) { in regmap_add_irq_chip_fwnode()
1059 for (i = 0; i < chip->num_config_bases; i++) in regmap_add_irq_chip_fwnode()
1060 kfree(d->config_buf[i]); in regmap_add_irq_chip_fwnode()
1061 kfree(d->config_buf); in regmap_add_irq_chip_fwnode()
1069 * regmap_add_irq_chip() - Use standard regmap IRQ controller handling
1075 * @chip: Configuration for the interrupt controller.
1076 * @data: Runtime data structure for the controller, allocated on success.
1078 * Returns 0 on success or an errno on failure.
1084 int irq_base, const struct regmap_irq_chip *chip, in regmap_add_irq_chip() argument
1087 return regmap_add_irq_chip_fwnode(dev_fwnode(map->dev), map, irq, in regmap_add_irq_chip()
1088 irq_flags, irq_base, chip, data); in regmap_add_irq_chip()
1093 * regmap_del_irq_chip() - Stop interrupt handling for a regmap IRQ chip
1098 * This function also disposes of all mapped IRQs on the chip.
1111 for (hwirq = 0; hwirq < d->chip->num_irqs; hwirq++) { in regmap_del_irq_chip()
1113 if (!d->chip->irqs[hwirq].mask) in regmap_del_irq_chip()
1117 * Find the virtual irq of hwirq on chip and if it is in regmap_del_irq_chip()
1120 virq = irq_find_mapping(d->domain, hwirq); in regmap_del_irq_chip()
1125 irq_domain_remove(d->domain); in regmap_del_irq_chip()
1126 kfree(d->type_buf); in regmap_del_irq_chip()
1127 kfree(d->type_buf_def); in regmap_del_irq_chip()
1128 kfree(d->wake_buf); in regmap_del_irq_chip()
1129 kfree(d->mask_buf_def); in regmap_del_irq_chip()
1130 kfree(d->mask_buf); in regmap_del_irq_chip()
1131 kfree(d->status_reg_buf); in regmap_del_irq_chip()
1132 kfree(d->status_buf); in regmap_del_irq_chip()
1133 if (d->config_buf) { in regmap_del_irq_chip()
1134 for (i = 0; i < d->chip->num_config_bases; i++) in regmap_del_irq_chip()
1135 kfree(d->config_buf[i]); in regmap_del_irq_chip()
1136 kfree(d->config_buf); in regmap_del_irq_chip()
1146 regmap_del_irq_chip(d->irq, d); in devm_regmap_irq_chip_release()
1162 * devm_regmap_add_irq_chip_fwnode() - Resource managed regmap_add_irq_chip_fwnode()
1164 * @dev: The device pointer on which irq_chip belongs to.
1170 * @chip: Configuration for the interrupt controller.
1171 * @data: Runtime data structure for the controller, allocated on success
1173 * Returns 0 on success or an errno on failure.
1182 const struct regmap_irq_chip *chip, in devm_regmap_add_irq_chip_fwnode() argument
1191 return -ENOMEM; in devm_regmap_add_irq_chip_fwnode()
1194 chip, &d); in devm_regmap_add_irq_chip_fwnode()
1208 * devm_regmap_add_irq_chip() - Resource managed regmap_add_irq_chip()
1210 * @dev: The device pointer on which irq_chip belongs to.
1215 * @chip: Configuration for the interrupt controller.
1216 * @data: Runtime data structure for the controller, allocated on success
1218 * Returns 0 on success or an errno on failure.
1225 const struct regmap_irq_chip *chip, in devm_regmap_add_irq_chip() argument
1228 return devm_regmap_add_irq_chip_fwnode(dev, dev_fwnode(map->dev), map, in devm_regmap_add_irq_chip()
1229 irq, irq_flags, irq_base, chip, in devm_regmap_add_irq_chip()
1235 * devm_regmap_del_irq_chip() - Resource managed regmap_del_irq_chip()
1248 WARN_ON(irq != data->irq); in devm_regmap_del_irq_chip()
1258 * regmap_irq_chip_get_base() - Retrieve interrupt base for a regmap IRQ chip
1260 * @data: regmap irq controller to operate on.
1266 WARN_ON(!data->irq_base); in regmap_irq_chip_get_base()
1267 return data->irq_base; in regmap_irq_chip_get_base()
1272 * regmap_irq_get_virq() - Map an interrupt on a chip to a virtual IRQ
1274 * @data: regmap irq controller to operate on.
1275 * @irq: index of the interrupt requested in the chip IRQs.
1282 if (!data->chip->irqs[irq].mask) in regmap_irq_get_virq()
1283 return -EINVAL; in regmap_irq_get_virq()
1285 return irq_create_mapping(data->domain, irq); in regmap_irq_get_virq()
1290 * regmap_irq_get_domain() - Retrieve the irq_domain for the chip
1292 * @data: regmap_irq controller to operate on.
1302 return data->domain; in regmap_irq_get_domain()