Lines Matching refs:iadev
75 static void desc_dbg(IADEV *iadev);
576 IADEV *iadev; in ia_cbrVc_close() local
580 iadev = INPH_IA_DEV(vcc->dev); in ia_cbrVc_close()
581 iadev->NumEnabledCBR--; in ia_cbrVc_close()
582 SchedTbl = (u16*)(iadev->seg_ram+CBR_SCHED_TABLE*iadev->memSize); in ia_cbrVc_close()
583 if (iadev->NumEnabledCBR == 0) { in ia_cbrVc_close()
584 writew((UBR_EN | ABR_EN | (0x23 << 2)), iadev->seg_reg+STPARMS); in ia_cbrVc_close()
588 for (i=0; i < iadev->CbrTotEntries; i++) in ia_cbrVc_close()
591 iadev->CbrRemEntries++; in ia_cbrVc_close()
600 static int ia_avail_descs(IADEV *iadev) { in ia_avail_descs() argument
602 ia_hack_tcq(iadev); in ia_avail_descs()
603 if (iadev->host_tcq_wr >= iadev->ffL.tcq_rd) in ia_avail_descs()
604 tmp = (iadev->host_tcq_wr - iadev->ffL.tcq_rd) / 2; in ia_avail_descs()
606 tmp = (iadev->ffL.tcq_ed - iadev->ffL.tcq_rd + 2 + iadev->host_tcq_wr - in ia_avail_descs()
607 iadev->ffL.tcq_st) / 2; in ia_avail_descs()
613 static int ia_que_tx (IADEV *iadev) { in ia_que_tx() argument
617 num_desc = ia_avail_descs(iadev); in ia_que_tx()
619 while (num_desc && (skb = skb_dequeue(&iadev->tx_backlog))) { in ia_que_tx()
631 skb_queue_head(&iadev->tx_backlog, skb); in ia_que_tx()
638 static void ia_tx_poll (IADEV *iadev) { in ia_tx_poll() argument
644 ia_hack_tcq(iadev); in ia_tx_poll()
645 while ( (rtne = ia_deque_rtn_q(&iadev->tx_return_q))) { in ia_tx_poll()
683 ia_enque_head_rtn_q (&iadev->tx_return_q, rtne); in ia_tx_poll()
695 ia_que_tx(iadev); in ia_tx_poll()
700 static void ia_eeprom_put (IADEV *iadev, u32 addr, u_short val)
722 t = readl(iadev->reg+IPHASE5575_EEPROM_ACCESS);
724 t = readl(iadev->reg+IPHASE5575_EEPROM_ACCESS);
736 static u16 ia_eeprom_get (IADEV *iadev, u32 addr) in ia_eeprom_get() argument
760 static void ia_hw_type(IADEV *iadev) { argument
761 u_short memType = ia_eeprom_get(iadev, 25);
762 iadev->memType = memType;
764 iadev->num_tx_desc = IA_TX_BUF;
765 iadev->tx_buf_sz = IA_TX_BUF_SZ;
766 iadev->num_rx_desc = IA_RX_BUF;
767 iadev->rx_buf_sz = IA_RX_BUF_SZ;
770 iadev->num_tx_desc = IA_TX_BUF / 2;
772 iadev->num_tx_desc = IA_TX_BUF;
773 iadev->tx_buf_sz = IA_TX_BUF_SZ;
775 iadev->num_rx_desc = IA_RX_BUF / 2;
777 iadev->num_rx_desc = IA_RX_BUF;
778 iadev->rx_buf_sz = IA_RX_BUF_SZ;
782 iadev->num_tx_desc = IA_TX_BUF / 8;
784 iadev->num_tx_desc = IA_TX_BUF;
785 iadev->tx_buf_sz = IA_TX_BUF_SZ;
787 iadev->num_rx_desc = IA_RX_BUF / 8;
789 iadev->num_rx_desc = IA_RX_BUF;
790 iadev->rx_buf_sz = IA_RX_BUF_SZ;
792 iadev->rx_pkt_ram = TX_PACKET_RAM + (iadev->num_tx_desc * iadev->tx_buf_sz);
794 iadev->num_tx_desc, iadev->tx_buf_sz, iadev->num_rx_desc,
795 iadev->rx_buf_sz, iadev->rx_pkt_ram);)
799 iadev->phy_type = PHY_OC3C_S;
801 iadev->phy_type = PHY_UTP155;
803 iadev->phy_type = PHY_OC3C_M;
806 iadev->phy_type = memType & FE_MASK;
808 memType,iadev->phy_type);)
809 if (iadev->phy_type == FE_25MBIT_PHY)
810 iadev->LineRate = (u32)(((25600000/8)*26)/(27*53));
811 else if (iadev->phy_type == FE_DS3_PHY)
812 iadev->LineRate = (u32)(((44736000/8)*26)/(27*53));
813 else if (iadev->phy_type == FE_E3_PHY)
814 iadev->LineRate = (u32)(((34368000/8)*26)/(27*53));
816 iadev->LineRate = (u32)(ATM_OC3_PCR);
817 IF_INIT(printk("iadev->LineRate = %d \n", iadev->LineRate);)
831 static void ia_frontend_intr(struct iadev_priv *iadev) argument
835 if (iadev->phy_type & FE_25MBIT_PHY) {
836 status = ia_phy_read32(iadev, MB25_INTR_STATUS);
837 iadev->carrier_detect = (status & MB25_IS_GSB) ? 1 : 0;
838 } else if (iadev->phy_type & FE_DS3_PHY) {
839 ia_phy_read32(iadev, SUNI_DS3_FRM_INTR_STAT);
840 status = ia_phy_read32(iadev, SUNI_DS3_FRM_STAT);
841 iadev->carrier_detect = (status & SUNI_DS3_LOSV) ? 0 : 1;
842 } else if (iadev->phy_type & FE_E3_PHY) {
843 ia_phy_read32(iadev, SUNI_E3_FRM_MAINT_INTR_IND);
844 status = ia_phy_read32(iadev, SUNI_E3_FRM_FRAM_INTR_IND_STAT);
845 iadev->carrier_detect = (status & SUNI_E3_LOS) ? 0 : 1;
847 status = ia_phy_read32(iadev, SUNI_RSOP_STATUS);
848 iadev->carrier_detect = (status & SUNI_LOSV) ? 0 : 1;
852 iadev->carrier_detect ? "detected" : "lost signal");
855 static void ia_mb25_init(struct iadev_priv *iadev) argument
860 ia_phy_write32(iadev, MB25_MASTER_CTRL, MB25_MC_DRIC | MB25_MC_DREC);
861 ia_phy_write32(iadev, MB25_DIAG_CONTROL, 0);
863 iadev->carrier_detect =
864 (ia_phy_read32(iadev, MB25_INTR_STATUS) & MB25_IS_GSB) ? 1 : 0;
872 static void ia_phy_write(struct iadev_priv *iadev, argument
876 ia_phy_write32(iadev, regs->reg, regs->val);
881 static void ia_suni_pm7345_init_ds3(struct iadev_priv *iadev) argument
893 status = ia_phy_read32(iadev, SUNI_DS3_FRM_STAT);
894 iadev->carrier_detect = (status & SUNI_DS3_LOSV) ? 0 : 1;
896 ia_phy_write(iadev, suni_ds3_init, ARRAY_SIZE(suni_ds3_init));
899 static void ia_suni_pm7345_init_e3(struct iadev_priv *iadev) argument
914 status = ia_phy_read32(iadev, SUNI_E3_FRM_FRAM_INTR_IND_STAT);
915 iadev->carrier_detect = (status & SUNI_E3_LOS) ? 0 : 1;
916 ia_phy_write(iadev, suni_e3_init, ARRAY_SIZE(suni_e3_init));
919 static void ia_suni_pm7345_init(struct iadev_priv *iadev) argument
957 if (iadev->phy_type & FE_DS3_PHY)
958 ia_suni_pm7345_init_ds3(iadev);
960 ia_suni_pm7345_init_e3(iadev);
962 ia_phy_write(iadev, suni_init, ARRAY_SIZE(suni_init));
964 ia_phy_write32(iadev, SUNI_CONFIG, ia_phy_read32(iadev, SUNI_CONFIG) &
1017 RAM_BASE*((iadev->mem)/(128 * 1024))
1019 IPHASE5575_FRAG_CONTROL_RAM_BASE*((iadev->mem)/(128 * 1024))
1021 IPHASE5575_REASS_CONTROL_RAM_BASE*((iadev->mem)/(128 * 1024))
1026 static void desc_dbg(IADEV *iadev) { argument
1032 tcq_wr_ptr = readw(iadev->seg_reg+TCQ_WR_PTR);
1034 tcq_wr_ptr, readw(iadev->seg_ram+tcq_wr_ptr),
1035 readw(iadev->seg_ram+tcq_wr_ptr-2));
1036 printk(" host_tcq_wr = 0x%x host_tcq_rd = 0x%x \n", iadev->host_tcq_wr,
1037 iadev->ffL.tcq_rd);
1038 tcq_st_ptr = readw(iadev->seg_reg+TCQ_ST_ADR);
1039 tcq_ed_ptr = readw(iadev->seg_reg+TCQ_ED_ADR);
1043 tmp = iadev->seg_ram+tcq_st_ptr;
1047 for(i=0; i <iadev->num_tx_desc; i++)
1048 printk("Desc_tbl[%d] = %d \n", i, iadev->desc_tbl[i].timestamp);
1057 IADEV *iadev;
1062 iadev = INPH_IA_DEV(dev);
1063 state = readl(iadev->reass_reg + STATE_REG) & 0xffff;
1066 excpq_rd_ptr = readw(iadev->reass_reg + EXCP_Q_RD_PTR) & 0xffff;
1068 if (excpq_rd_ptr == *(u16*)(iadev->reass_reg + EXCP_Q_WR_PTR))
1071 vci = readw(iadev->reass_ram+excpq_rd_ptr);
1072 error = readw(iadev->reass_ram+excpq_rd_ptr+2) & 0x0007;
1075 if (excpq_rd_ptr > (readw(iadev->reass_reg + EXCP_Q_ED_ADR)& 0xffff))
1076 excpq_rd_ptr = readw(iadev->reass_reg + EXCP_Q_ST_ADR)& 0xffff;
1077 writew( excpq_rd_ptr, iadev->reass_reg + EXCP_Q_RD_PTR);
1078 state = readl(iadev->reass_reg + STATE_REG) & 0xffff;
1085 IADEV *iadev; local
1086 iadev = INPH_IA_DEV(dev);
1087 writew(desc, iadev->reass_ram+iadev->rfL.fdq_wr);
1088 iadev->rfL.fdq_wr +=2;
1089 if (iadev->rfL.fdq_wr > iadev->rfL.fdq_ed)
1090 iadev->rfL.fdq_wr = iadev->rfL.fdq_st;
1091 writew(iadev->rfL.fdq_wr, iadev->reass_reg+FREEQ_WR_PTR);
1097 IADEV *iadev; local
1107 iadev = INPH_IA_DEV(dev);
1108 if (iadev->rfL.pcq_rd == (readw(iadev->reass_reg+PCQ_WR_PTR)&0xffff))
1114 desc = readw(iadev->reass_ram+iadev->rfL.pcq_rd) & 0x1fff;
1116 iadev->reass_ram, iadev->rfL.pcq_rd, desc);
1118 readw(iadev->reass_reg+PCQ_WR_PTR)&0xffff);)
1120 if ( iadev->rfL.pcq_rd== iadev->rfL.pcq_ed)
1121 iadev->rfL.pcq_rd = iadev->rfL.pcq_st;
1123 iadev->rfL.pcq_rd += 2;
1124 writew(iadev->rfL.pcq_rd, iadev->reass_reg+PCQ_RD_PTR);
1129 buf_desc_ptr = iadev->RX_DESC_BASE_ADDR;
1132 if (!desc || (desc > iadev->num_rx_desc) ||
1133 ((buf_desc_ptr->vc_index & 0xffff) >= iadev->num_vc)) {
1138 vcc = iadev->rx_open[buf_desc_ptr->vc_index & 0xffff];
1172 if (len > iadev->rx_buf_sz) {
1173 printk("Over %d bytes sdu received, dropped!!!\n", iadev->rx_buf_sz);
1187 skb_queue_tail(&iadev->rx_dma_q, skb);
1190 wr_ptr = iadev->rx_dle_q.write;
1191 wr_ptr->sys_pkt_addr = dma_map_single(&iadev->pci->dev, skb->data,
1198 if(++wr_ptr == iadev->rx_dle_q.end)
1199 wr_ptr = iadev->rx_dle_q.start;
1200 iadev->rx_dle_q.write = wr_ptr;
1203 writel(1, iadev->dma+IPHASE5575_RX_COUNTER);
1212 IADEV *iadev; local
1216 iadev = INPH_IA_DEV(dev);
1217 status = readl(iadev->reass_reg+REASS_INTR_STATUS_REG) & 0xffff;
1227 state = readl(iadev->reass_reg + STATE_REG) & 0xffff;
1232 state = readl(iadev->reass_reg + STATE_REG) & 0xffff;
1234 iadev->rxing = 1;
1238 if (iadev->rxing) {
1239 iadev->rx_tmp_cnt = iadev->rx_pkt_cnt;
1240 iadev->rx_tmp_jif = jiffies;
1241 iadev->rxing = 0;
1243 else if ((time_after(jiffies, iadev->rx_tmp_jif + 50)) &&
1244 ((iadev->rx_pkt_cnt - iadev->rx_tmp_cnt) == 0)) {
1245 for (i = 1; i <= iadev->num_rx_desc; i++)
1248 writew( ~(RX_FREEQ_EMPT|RX_EXCP_RCVD),iadev->reass_reg+REASS_MASK_REG);
1249 iadev->rxing = 1;
1274 IADEV *iadev; local
1282 iadev = INPH_IA_DEV(dev);
1289 dle = iadev->rx_dle_q.read;
1290 dle_lp = readl(iadev->dma+IPHASE5575_RX_LIST_ADDR) & (sizeof(struct dle)*DLE_ENTRIES - 1);
1291 cur_dle = (struct dle*)(iadev->rx_dle_q.start + (dle_lp >> 4));
1295 skb = skb_dequeue(&iadev->rx_dma_q);
1312 dma_unmap_single(&iadev->pci->dev, iadev->rx_dle_q.write->sys_pkt_addr,
1333 if ((length > iadev->rx_buf_sz) || (length >
1353 iadev->rx_pkt_cnt++;
1356 if (++dle == iadev->rx_dle_q.end)
1357 dle = iadev->rx_dle_q.start;
1359 iadev->rx_dle_q.read = dle;
1363 if (!iadev->rxing) {
1364 state = readl(iadev->reass_reg + STATE_REG) & 0xffff;
1366 state = readl(iadev->reass_reg + REASS_MASK_REG) & 0xffff;
1368 iadev->reass_reg+REASS_MASK_REG);
1369 iadev->rxing++;
1377 IADEV *iadev; local
1383 iadev = INPH_IA_DEV(vcc->dev);
1385 if (iadev->phy_type & FE_25MBIT_PHY) {
1392 vc_table = iadev->reass_ram+RX_VC_TABLE*iadev->memSize;
1403 init_abr_vc(iadev, &srv_p);
1404 ia_open_abr_vc(iadev, &srv_p, vcc, 0);
1407 reass_ptr = iadev->reass_ram+REASS_TABLE*iadev->memSize;
1412 if (iadev->rx_open[vcc->vci])
1415 iadev->rx_open[vcc->vci] = vcc;
1421 IADEV *iadev; local
1432 iadev = INPH_IA_DEV(dev);
1436 dle_addr = dma_alloc_coherent(&iadev->pci->dev, DLE_TOTAL_SIZE,
1437 &iadev->rx_dle_dma, GFP_KERNEL);
1442 iadev->rx_dle_q.start = (struct dle *)dle_addr;
1443 iadev->rx_dle_q.read = iadev->rx_dle_q.start;
1444 iadev->rx_dle_q.write = iadev->rx_dle_q.start;
1445 iadev->rx_dle_q.end = (struct dle*)((unsigned long)dle_addr+sizeof(struct dle)*DLE_ENTRIES);
1451 writel(iadev->rx_dle_dma & 0xfffff000,
1452 iadev->dma + IPHASE5575_RX_LIST_ADDR);
1454 iadev->dma+IPHASE5575_TX_LIST_ADDR,
1455 readl(iadev->dma + IPHASE5575_TX_LIST_ADDR));
1457 iadev->dma+IPHASE5575_RX_LIST_ADDR,
1458 readl(iadev->dma + IPHASE5575_RX_LIST_ADDR));)
1460 writew(0xffff, iadev->reass_reg+REASS_MASK_REG);
1461 writew(0, iadev->reass_reg+MODE_REG);
1462 writew(RESET_REASS, iadev->reass_reg+REASS_COMMAND_REG);
1478 writew(RX_DESC_BASE >> 16, iadev->reass_reg+REASS_DESC_BASE);
1480 writew(iadev->rx_buf_sz, iadev->reass_reg+BUF_SIZE);
1483 iadev->RX_DESC_BASE_ADDR = iadev->reass_ram+RX_DESC_BASE*iadev->memSize;
1484 buf_desc_ptr = iadev->RX_DESC_BASE_ADDR;
1487 rx_pkt_start = iadev->rx_pkt_ram;
1488 for(i=1; i<=iadev->num_rx_desc; i++)
1494 rx_pkt_start += iadev->rx_buf_sz;
1497 i = FREE_BUF_DESC_Q*iadev->memSize;
1498 writew(i >> 16, iadev->reass_reg+REASS_QUEUE_BASE);
1499 writew(i, iadev->reass_reg+FREEQ_ST_ADR);
1500 writew(i+iadev->num_rx_desc*sizeof(u_short),
1501 iadev->reass_reg+FREEQ_ED_ADR);
1502 writew(i, iadev->reass_reg+FREEQ_RD_PTR);
1503 writew(i+iadev->num_rx_desc*sizeof(u_short),
1504 iadev->reass_reg+FREEQ_WR_PTR);
1506 freeq_st_adr = readw(iadev->reass_reg+FREEQ_ST_ADR);
1507 freeq_start = (u_short *)(iadev->reass_ram+freeq_st_adr);
1508 for(i=1; i<=iadev->num_rx_desc; i++)
1515 i = (PKT_COMP_Q * iadev->memSize) & 0xffff;
1516 writew(i, iadev->reass_reg+PCQ_ST_ADR);
1517 writew(i+iadev->num_vc*sizeof(u_short), iadev->reass_reg+PCQ_ED_ADR);
1518 writew(i, iadev->reass_reg+PCQ_RD_PTR);
1519 writew(i, iadev->reass_reg+PCQ_WR_PTR);
1522 i = (EXCEPTION_Q * iadev->memSize) & 0xffff;
1523 writew(i, iadev->reass_reg+EXCP_Q_ST_ADR);
1525 iadev->reass_reg+EXCP_Q_ED_ADR);
1526 writew(i, iadev->reass_reg+EXCP_Q_RD_PTR);
1527 writew(i, iadev->reass_reg+EXCP_Q_WR_PTR);
1530 iadev->rfL.fdq_st = readw(iadev->reass_reg+FREEQ_ST_ADR) & 0xffff;
1531 iadev->rfL.fdq_ed = readw(iadev->reass_reg+FREEQ_ED_ADR) & 0xffff ;
1532 iadev->rfL.fdq_rd = readw(iadev->reass_reg+FREEQ_RD_PTR) & 0xffff;
1533 iadev->rfL.fdq_wr = readw(iadev->reass_reg+FREEQ_WR_PTR) & 0xffff;
1534 iadev->rfL.pcq_st = readw(iadev->reass_reg+PCQ_ST_ADR) & 0xffff;
1535 iadev->rfL.pcq_ed = readw(iadev->reass_reg+PCQ_ED_ADR) & 0xffff;
1536 iadev->rfL.pcq_rd = readw(iadev->reass_reg+PCQ_RD_PTR) & 0xffff;
1537 iadev->rfL.pcq_wr = readw(iadev->reass_reg+PCQ_WR_PTR) & 0xffff;
1540 iadev->rfL.pcq_st, iadev->rfL.pcq_ed, iadev->rfL.pcq_rd,
1541 iadev->rfL.pcq_wr);)
1551 i = REASS_TABLE * iadev->memSize;
1552 writew((i >> 3), iadev->reass_reg+REASS_TABLE_BASE);
1554 reass_table = (u16 *)(iadev->reass_ram+i);
1555 j = REASS_TABLE_SZ * iadev->memSize;
1560 while (i != iadev->num_vc) {
1564 i = RX_VC_TABLE * iadev->memSize;
1565 writew(((i>>3) & 0xfff8) | vcsize_sel, iadev->reass_reg+VC_LKUP_BASE);
1566 vc_table = (u16 *)(iadev->reass_ram+RX_VC_TABLE*iadev->memSize);
1567 j = RX_VC_TABLE_SZ * iadev->memSize;
1579 i = ABR_VC_TABLE * iadev->memSize;
1580 writew(i >> 3, iadev->reass_reg+ABR_LKUP_BASE);
1582 i = ABR_VC_TABLE * iadev->memSize;
1583 abr_vc_table = (struct abr_vc_table *)(iadev->reass_ram+i);
1584 j = REASS_TABLE_SZ * iadev->memSize;
1595 writew(0xff00, iadev->reass_reg+VP_FILTER);
1596 writew(0, iadev->reass_reg+XTRA_RM_OFFSET);
1597 writew(0x1, iadev->reass_reg+PROTOCOL_ID);
1603 writew(0xF6F8, iadev->reass_reg+PKT_TM_CNT );
1608 writew(i, iadev->reass_reg+TMOUT_RANGE);
1611 for(i=0; i<iadev->num_tx_desc;i++)
1612 iadev->desc_tbl[i].timestamp = 0;
1615 readw(iadev->reass_reg+REASS_INTR_STATUS_REG);
1618 writew(~(RX_FREEQ_EMPT|RX_PKT_RCVD), iadev->reass_reg+REASS_MASK_REG);
1620 skb_queue_head_init(&iadev->rx_dma_q);
1621 iadev->rx_free_desc_qhead = NULL;
1623 iadev->rx_open = kcalloc(iadev->num_vc, sizeof(void *), GFP_KERNEL);
1624 if (!iadev->rx_open) {
1630 iadev->rxing = 1;
1631 iadev->rx_pkt_cnt = 0;
1633 writew(R_ONLINE, iadev->reass_reg+MODE_REG);
1637 dma_free_coherent(&iadev->pci->dev, DLE_TOTAL_SIZE, iadev->rx_dle_q.start,
1638 iadev->rx_dle_dma);
1661 IADEV *iadev; local
1665 iadev = INPH_IA_DEV(dev);
1667 status = readl(iadev->seg_reg+SEG_INTR_STATUS_REG);
1671 spin_lock_irqsave(&iadev->tx_lock, flags);
1672 ia_tx_poll(iadev);
1673 spin_unlock_irqrestore(&iadev->tx_lock, flags);
1674 writew(TRANSMIT_DONE, iadev->seg_reg+SEG_INTR_STATUS_REG);
1675 if (iadev->close_pending)
1676 wake_up(&iadev->close_wait);
1686 IADEV *iadev; local
1694 iadev = INPH_IA_DEV(dev);
1695 spin_lock_irqsave(&iadev->tx_lock, flags);
1696 dle = iadev->tx_dle_q.read;
1697 dle_lp = readl(iadev->dma+IPHASE5575_TX_LIST_ADDR) &
1699 cur_dle = (struct dle*)(iadev->tx_dle_q.start + (dle_lp >> 4));
1703 skb = skb_dequeue(&iadev->tx_dma_q);
1707 if (!((dle - iadev->tx_dle_q.start)%(2*sizeof(struct dle)))) {
1708 dma_unmap_single(&iadev->pci->dev, dle->sys_pkt_addr, skb->len,
1714 spin_unlock_irqrestore(&iadev->tx_lock, flags);
1722 spin_unlock_irqrestore(&iadev->tx_lock, flags);
1726 if (vcc->qos.txtp.pcr >= iadev->rate_limit) {
1740 if (++dle == iadev->tx_dle_q.end)
1741 dle = iadev->tx_dle_q.start;
1743 iadev->tx_dle_q.read = dle;
1744 spin_unlock_irqrestore(&iadev->tx_lock, flags);
1750 IADEV *iadev; local
1756 iadev = INPH_IA_DEV(vcc->dev);
1758 if (iadev->phy_type & FE_25MBIT_PHY) {
1771 (iadev->tx_buf_sz - sizeof(struct cpcs_trailer))){
1773 vcc->qos.txtp.max_sdu,iadev->tx_buf_sz);
1783 vcc->qos.txtp.pcr = iadev->LineRate;
1785 vcc->qos.txtp.pcr = iadev->LineRate;
1788 if (vcc->qos.txtp.pcr > iadev->LineRate)
1789 vcc->qos.txtp.pcr = iadev->LineRate;
1792 if (ia_vcc->pcr > (iadev->LineRate / 6) ) ia_vcc->ltimeout = HZ / 10;
1793 else if (ia_vcc->pcr > (iadev->LineRate / 130)) ia_vcc->ltimeout = HZ;
1796 if (ia_vcc->pcr < iadev->rate_limit)
1798 if (ia_vcc->pcr < iadev->rate_limit) {
1813 vc = (struct main_vc *)iadev->MAIN_VC_TABLE_ADDR;
1814 evc = (struct ext_vc *)iadev->EXT_VC_TABLE_ADDR;
1833 vc->acr = cellrate_to_float(iadev->LineRate);
1842 init_abr_vc(iadev, &srv_p);
1846 int tmpsum = iadev->sum_mcr+iadev->sum_cbr+vcc->qos.txtp.min_pcr;
1847 if (tmpsum > iadev->LineRate)
1850 iadev->sum_mcr += vcc->qos.txtp.min_pcr;
1875 ia_open_abr_vc(iadev, &srv_p, vcc, 1);
1877 if (iadev->phy_type & FE_25MBIT_PHY) {
1881 if (vcc->qos.txtp.max_pcr > iadev->LineRate) {
1887 if ((ret = ia_cbr_setup (iadev, vcc)) < 0) {
1894 iadev->testTable[vcc->vci]->vc_status |= VC_ACTIVE;
1902 IADEV *iadev; local
1916 iadev = INPH_IA_DEV(dev);
1917 spin_lock_init(&iadev->tx_lock);
1920 readw(iadev->seg_reg+SEG_MASK_REG));)
1923 dle_addr = dma_alloc_coherent(&iadev->pci->dev, DLE_TOTAL_SIZE,
1924 &iadev->tx_dle_dma, GFP_KERNEL);
1929 iadev->tx_dle_q.start = (struct dle*)dle_addr;
1930 iadev->tx_dle_q.read = iadev->tx_dle_q.start;
1931 iadev->tx_dle_q.write = iadev->tx_dle_q.start;
1932 iadev->tx_dle_q.end = (struct dle*)((unsigned long)dle_addr+sizeof(struct dle)*DLE_ENTRIES);
1935 writel(iadev->tx_dle_dma & 0xfffff000,
1936 iadev->dma + IPHASE5575_TX_LIST_ADDR);
1937 writew(0xffff, iadev->seg_reg+SEG_MASK_REG);
1938 writew(0, iadev->seg_reg+MODE_REG_0);
1939 writew(RESET_SEG, iadev->seg_reg+SEG_COMMAND_REG);
1940 iadev->MAIN_VC_TABLE_ADDR = iadev->seg_ram+MAIN_VC_TABLE*iadev->memSize;
1941 iadev->EXT_VC_TABLE_ADDR = iadev->seg_ram+EXT_VC_TABLE*iadev->memSize;
1942 iadev->ABR_SCHED_TABLE_ADDR=iadev->seg_ram+ABR_SCHED_TABLE*iadev->memSize;
1964 writew(TX_DESC_BASE, iadev->seg_reg+SEG_DESC_BASE);
1967 buf_desc_ptr =(struct tx_buf_desc *)(iadev->seg_ram+TX_DESC_BASE);
1971 for(i=1; i<=iadev->num_tx_desc; i++)
1978 tx_pkt_start += iadev->tx_buf_sz;
1980 iadev->tx_buf = kmalloc_array(iadev->num_tx_desc,
1981 sizeof(*iadev->tx_buf),
1983 if (!iadev->tx_buf) {
1987 for (i= 0; i< iadev->num_tx_desc; i++)
1996 iadev->tx_buf[i].cpcs = cpcs;
1997 iadev->tx_buf[i].dma_addr = dma_map_single(&iadev->pci->dev,
2002 iadev->desc_tbl = kmalloc_array(iadev->num_tx_desc,
2003 sizeof(*iadev->desc_tbl),
2005 if (!iadev->desc_tbl) {
2011 i = TX_COMP_Q * iadev->memSize;
2012 writew(i >> 16, iadev->seg_reg+SEG_QUEUE_BASE);
2015 writew(i, iadev->seg_reg+TCQ_ST_ADR);
2016 writew(i, iadev->seg_reg+TCQ_RD_PTR);
2017 writew(i+iadev->num_tx_desc*sizeof(u_short),iadev->seg_reg+TCQ_WR_PTR);
2018 iadev->host_tcq_wr = i + iadev->num_tx_desc*sizeof(u_short);
2019 writew(i+2 * iadev->num_tx_desc * sizeof(u_short),
2020 iadev->seg_reg+TCQ_ED_ADR);
2022 tcq_st_adr = readw(iadev->seg_reg+TCQ_ST_ADR);
2023 tcq_start = (u_short *)(iadev->seg_ram+tcq_st_adr);
2024 for(i=1; i<=iadev->num_tx_desc; i++)
2031 i = PKT_RDY_Q * iadev->memSize;
2032 writew(i, iadev->seg_reg+PRQ_ST_ADR);
2033 writew(i+2 * iadev->num_tx_desc * sizeof(u_short),
2034 iadev->seg_reg+PRQ_ED_ADR);
2035 writew(i, iadev->seg_reg+PRQ_RD_PTR);
2036 writew(i, iadev->seg_reg+PRQ_WR_PTR);
2039 iadev->ffL.prq_st = readw(iadev->seg_reg+PRQ_ST_ADR) & 0xffff;
2040 iadev->ffL.prq_ed = readw(iadev->seg_reg+PRQ_ED_ADR) & 0xffff;
2041 iadev->ffL.prq_wr = readw(iadev->seg_reg+PRQ_WR_PTR) & 0xffff;
2043 iadev->ffL.tcq_st = readw(iadev->seg_reg+TCQ_ST_ADR) & 0xffff;
2044 iadev->ffL.tcq_ed = readw(iadev->seg_reg+TCQ_ED_ADR) & 0xffff;
2045 iadev->ffL.tcq_rd = readw(iadev->seg_reg+TCQ_RD_PTR) & 0xffff;
2049 prq_st_adr = readw(iadev->seg_reg+PRQ_ST_ADR);
2050 prq_start = (u_short *)(iadev->seg_ram+prq_st_adr);
2051 for(i=1; i<=iadev->num_tx_desc; i++)
2059 writew(0,iadev->seg_reg+CBR_PTR_BASE);
2061 tmp16 = (iadev->seg_ram+CBR_SCHED_TABLE*iadev->memSize)>>17;
2063 writew(tmp16,iadev->seg_reg+CBR_PTR_BASE);
2067 readw(iadev->seg_reg+CBR_PTR_BASE));)
2068 tmp16 = (CBR_SCHED_TABLE*iadev->memSize) >> 1;
2069 writew(tmp16, iadev->seg_reg+CBR_TAB_BEG);
2071 readw(iadev->seg_reg+CBR_TAB_BEG));)
2072 writew(tmp16, iadev->seg_reg+CBR_TAB_END+1); // CBR_PTR;
2073 tmp16 = (CBR_SCHED_TABLE*iadev->memSize + iadev->num_vc*6 - 2) >> 1;
2074 writew(tmp16, iadev->seg_reg+CBR_TAB_END);
2076 iadev->seg_reg, readw(iadev->seg_reg+CBR_PTR_BASE));)
2078 readw(iadev->seg_reg+CBR_TAB_BEG), readw(iadev->seg_reg+CBR_TAB_END),
2079 readw(iadev->seg_reg+CBR_TAB_END+1));)
2082 memset_io(iadev->seg_ram+CBR_SCHED_TABLE*iadev->memSize,
2083 0, iadev->num_vc*6);
2084 iadev->CbrRemEntries = iadev->CbrTotEntries = iadev->num_vc*3;
2085 iadev->CbrEntryPt = 0;
2086 iadev->Granularity = MAX_ATM_155 / iadev->CbrTotEntries;
2087 iadev->NumEnabledCBR = 0;
2100 while (i != iadev->num_vc) {
2105 i = MAIN_VC_TABLE * iadev->memSize;
2106 writew(vcsize_sel | ((i >> 8) & 0xfff8),iadev->seg_reg+VCT_BASE);
2107 i = EXT_VC_TABLE * iadev->memSize;
2108 writew((i >> 8) & 0xfffe, iadev->seg_reg+VCTE_BASE);
2109 i = UBR_SCHED_TABLE * iadev->memSize;
2110 writew((i & 0xffff) >> 11, iadev->seg_reg+UBR_SBPTR_BASE);
2111 i = UBR_WAIT_Q * iadev->memSize;
2112 writew((i >> 7) & 0xffff, iadev->seg_reg+UBRWQ_BASE);
2113 memset((caddr_t)(iadev->seg_ram+UBR_SCHED_TABLE*iadev->memSize),
2114 0, iadev->num_vc*8);
2123 i = ABR_SCHED_TABLE * iadev->memSize;
2124 writew((i >> 11) & 0xffff, iadev->seg_reg+ABR_SBPTR_BASE);
2125 i = ABR_WAIT_Q * iadev->memSize;
2126 writew((i >> 7) & 0xffff, iadev->seg_reg+ABRWQ_BASE);
2128 i = ABR_SCHED_TABLE*iadev->memSize;
2129 memset((caddr_t)(iadev->seg_ram+i), 0, iadev->num_vc*4);
2130 vc = (struct main_vc *)iadev->MAIN_VC_TABLE_ADDR;
2131 evc = (struct ext_vc *)iadev->EXT_VC_TABLE_ADDR;
2132 iadev->testTable = kmalloc_array(iadev->num_vc,
2133 sizeof(*iadev->testTable),
2135 if (!iadev->testTable) {
2139 for(i=0; i<iadev->num_vc; i++)
2143 iadev->testTable[i] = kmalloc(sizeof(struct testTable_t),
2145 if (!iadev->testTable[i])
2147 iadev->testTable[i]->lastTime = 0;
2148 iadev->testTable[i]->fract = 0;
2149 iadev->testTable[i]->vc_status = VC_UBR;
2157 if (iadev->phy_type & FE_25MBIT_PHY) {
2158 writew(RATE25, iadev->seg_reg+MAXRATE);
2159 writew((UBR_EN | (0x23 << 2)), iadev->seg_reg+STPARMS);
2162 writew(cellrate_to_float(iadev->LineRate),iadev->seg_reg+MAXRATE);
2163 writew((UBR_EN | ABR_EN | (0x23 << 2)), iadev->seg_reg+STPARMS);
2166 writew(0, iadev->seg_reg+IDLEHEADHI);
2167 writew(0, iadev->seg_reg+IDLEHEADLO);
2170 writew(0xaa00, iadev->seg_reg+ABRUBR_ARB);
2172 iadev->close_pending = 0;
2173 init_waitqueue_head(&iadev->close_wait);
2174 init_waitqueue_head(&iadev->timeout_wait);
2175 skb_queue_head_init(&iadev->tx_dma_q);
2176 ia_init_rtn_q(&iadev->tx_return_q);
2179 writew(RM_TYPE_4_0, iadev->seg_reg+RM_TYPE);
2180 skb_queue_head_init (&iadev->tx_backlog);
2183 writew(MODE_REG_1_VAL, iadev->seg_reg+MODE_REG_1);
2186 writew(T_ONLINE, iadev->seg_reg+MODE_REG_0);
2189 readw(iadev->seg_reg+SEG_INTR_STATUS_REG);
2192 writew(~(TRANSMIT_DONE | TCQ_NOT_EMPTY), iadev->seg_reg+SEG_MASK_REG);
2193 writew(TRANSMIT_DONE, iadev->seg_reg+SEG_INTR_STATUS_REG);
2194 iadev->tx_pkt_cnt = 0;
2195 iadev->rate_limit = iadev->LineRate / 3;
2201 kfree(iadev->testTable[i]);
2202 kfree(iadev->testTable);
2204 kfree(iadev->desc_tbl);
2206 i = iadev->num_tx_desc;
2209 struct cpcs_trailer_desc *desc = iadev->tx_buf + i;
2211 dma_unmap_single(&iadev->pci->dev, desc->dma_addr,
2215 kfree(iadev->tx_buf);
2217 dma_free_coherent(&iadev->pci->dev, DLE_TOTAL_SIZE, iadev->tx_dle_q.start,
2218 iadev->tx_dle_dma);
2226 IADEV *iadev; local
2231 iadev = INPH_IA_DEV(dev);
2232 while( (status = readl(iadev->reg+IPHASE5575_BUS_STATUS_REG) & 0x7f))
2245 writel(STAT_DLERINT, iadev->reg + IPHASE5575_BUS_STATUS_REG);
2256 writel(STAT_DLETINT, iadev->reg + IPHASE5575_BUS_STATUS_REG);
2262 ia_frontend_intr(iadev);
2273 IADEV *iadev; local
2278 iadev = INPH_IA_DEV(dev);
2280 iadev->reg+IPHASE5575_MAC1)));
2281 mac2 = cpu_to_be16(le16_to_cpu(readl(iadev->reg+IPHASE5575_MAC2)));
2293 IADEV *iadev; local
2297 iadev = INPH_IA_DEV(dev);
2299 if ((error = pci_read_config_dword(iadev->pci,
2302 writel(0, iadev->reg+IPHASE5575_EXT_RESET);
2304 if ((error = pci_write_config_dword(iadev->pci,
2314 IADEV *iadev; local
2328 iadev = INPH_IA_DEV(dev);
2329 real_base = pci_resource_start (iadev->pci, 0);
2330 iadev->irq = iadev->pci->irq;
2332 error = pci_read_config_word(iadev->pci, PCI_COMMAND, &command);
2339 dev->number, iadev->pci->revision, real_base, iadev->irq);)
2343 iadev->pci_map_size = pci_resource_len(iadev->pci, 0);
2345 if (iadev->pci_map_size == 0x100000){
2346 iadev->num_vc = 4096;
2348 iadev->memSize = 4;
2350 else if (iadev->pci_map_size == 0x40000) {
2351 iadev->num_vc = 1024;
2352 iadev->memSize = 1;
2355 printk("Unknown pci_map_size = 0x%x\n", iadev->pci_map_size);
2358 IF_INIT(printk (DEV_LABEL "map size: %i\n", iadev->pci_map_size);)
2361 pci_set_master(iadev->pci);
2369 base = ioremap(real_base,iadev->pci_map_size); /* ioremap is not resolved ??? */
2378 dev->number, iadev->pci->revision, base, iadev->irq);)
2381 iadev->mem = iadev->pci_map_size /2;
2382 iadev->real_base = real_base;
2383 iadev->base = base;
2386 iadev->reg = base + REG_BASE;
2388 iadev->seg_reg = base + SEG_BASE;
2390 iadev->reass_reg = base + REASS_BASE;
2392 iadev->phy = base + PHY_BASE;
2393 iadev->dma = base + PHY_BASE;
2395 iadev->ram = base + ACTUAL_RAM_BASE;
2396 iadev->seg_ram = base + ACTUAL_SEG_RAM_BASE;
2397 iadev->reass_ram = base + ACTUAL_REASS_RAM_BASE;
2401 iadev->reg,iadev->seg_reg,iadev->reass_reg,
2402 iadev->phy, iadev->ram, iadev->seg_ram,
2403 iadev->reass_ram);)
2408 iounmap(iadev->base);
2418 iounmap(iadev->base);
2425 static void ia_update_stats(IADEV *iadev) { argument
2426 if (!iadev->carrier_detect)
2428 iadev->rx_cell_cnt += readw(iadev->reass_reg+CELL_CTR0)&0xffff;
2429 iadev->rx_cell_cnt += (readw(iadev->reass_reg+CELL_CTR1) & 0xffff) << 16;
2430 iadev->drop_rxpkt += readw(iadev->reass_reg + DRP_PKT_CNTR ) & 0xffff;
2431 iadev->drop_rxcell += readw(iadev->reass_reg + ERR_CNTR) & 0xffff;
2432 iadev->tx_cell_cnt += readw(iadev->seg_reg + CELL_CTR_LO_AUTO)&0xffff;
2433 iadev->tx_cell_cnt += (readw(iadev->seg_reg+CELL_CTR_HIGH_AUTO)&0xffff)<<16;
2478 static void ia_free_tx(IADEV *iadev) argument
2482 kfree(iadev->desc_tbl);
2483 for (i = 0; i < iadev->num_vc; i++)
2484 kfree(iadev->testTable[i]);
2485 kfree(iadev->testTable);
2486 for (i = 0; i < iadev->num_tx_desc; i++) {
2487 struct cpcs_trailer_desc *desc = iadev->tx_buf + i;
2489 dma_unmap_single(&iadev->pci->dev, desc->dma_addr,
2493 kfree(iadev->tx_buf);
2494 dma_free_coherent(&iadev->pci->dev, DLE_TOTAL_SIZE, iadev->tx_dle_q.start,
2495 iadev->tx_dle_dma);
2498 static void ia_free_rx(IADEV *iadev) argument
2500 kfree(iadev->rx_open);
2501 dma_free_coherent(&iadev->pci->dev, DLE_TOTAL_SIZE, iadev->rx_dle_q.start,
2502 iadev->rx_dle_dma);
2507 IADEV *iadev; local
2512 iadev = INPH_IA_DEV(dev);
2513 if (request_irq(iadev->irq, &ia_int, IRQF_SHARED, DEV_LABEL, dev)) {
2515 dev->number, iadev->irq);
2521 if ((error = pci_write_config_word(iadev->pci,
2536 readl(iadev->reg+IPHASE5575_BUS_CONTROL_REG));)
2537 ctrl_reg = readl(iadev->reg+IPHASE5575_BUS_CONTROL_REG);
2553 writel(ctrl_reg, iadev->reg+IPHASE5575_BUS_CONTROL_REG);
2556 readl(iadev->reg+IPHASE5575_BUS_CONTROL_REG));
2558 readl(iadev->reg+IPHASE5575_BUS_STATUS_REG));)
2560 ia_hw_type(iadev);
2568 ctrl_reg = readl(iadev->reg+IPHASE5575_BUS_CONTROL_REG);
2569 writel(ctrl_reg | CTRL_FE_RST, iadev->reg+IPHASE5575_BUS_CONTROL_REG);
2571 readl(iadev->reg+IPHASE5575_BUS_CONTROL_REG));)
2579 if (iadev->phy_type & FE_25MBIT_PHY)
2580 ia_mb25_init(iadev);
2581 else if (iadev->phy_type & (FE_DS3_PHY | FE_E3_PHY))
2582 ia_suni_pm7345_init(iadev);
2593 ia_frontend_intr(iadev);
2598 ia_free_rx(iadev);
2600 ia_free_tx(iadev);
2602 free_irq(iadev->irq, dev);
2611 IADEV *iadev; local
2617 iadev = INPH_IA_DEV(vcc->dev);
2627 iadev->close_pending++;
2628 prepare_to_wait(&iadev->timeout_wait, &wait, TASK_UNINTERRUPTIBLE);
2630 finish_wait(&iadev->timeout_wait, &wait);
2631 spin_lock_irqsave(&iadev->tx_lock, flags);
2632 while((skb = skb_dequeue(&iadev->tx_backlog))) {
2641 skb_queue_tail(&iadev->tx_backlog, skb);
2646 spin_unlock_irqrestore(&iadev->tx_lock, flags);
2647 wait_event_timeout(iadev->close_wait, (ia_vcc->vc_desc_cnt <= 0), closetime);
2648 spin_lock_irqsave(&iadev->tx_lock, flags);
2649 iadev->close_pending--;
2650 iadev->testTable[vcc->vci]->lastTime = 0;
2651 iadev->testTable[vcc->vci]->fract = 0;
2652 iadev->testTable[vcc->vci]->vc_status = VC_UBR;
2655 iadev->sum_mcr -= vcc->qos.txtp.min_pcr;
2659 iadev->sum_mcr -= ia_vcc->NumCbrEntry*iadev->Granularity;
2662 spin_unlock_irqrestore(&iadev->tx_lock, flags);
2667 vc_table = (u16 *)(iadev->reass_ram+REASS_TABLE*iadev->memSize);
2671 vc_table = (u16 *)(iadev->reass_ram+RX_VC_TABLE*iadev->memSize);
2676 (iadev->reass_ram+ABR_VC_TABLE*iadev->memSize);
2683 iadev->rx_open[vcc->vci] = NULL;
2755 IADEV *iadev; local
2770 iadev = ia_dev[board];
2779 if(put_user((u16)(readl(iadev->seg_reg+i) & 0xffff), tmps)) return -EFAULT;
2787 if(put_user((u16)(readl(iadev->reass_reg+i) & 0xffff), tmps)) return -EFAULT;
2804 ((u_int *)rfL)[i] = readl(iadev->reass_reg + i) & 0xffff;
2807 ((u_int *)ffL)[i] = readl(iadev->seg_reg + i) & 0xffff;
2821 desc_dbg(iadev);
2828 printk("skb = 0x%p\n", skb_peek(&iadev->tx_backlog));
2829 printk("rtn_q: 0x%p\n",ia_deque_rtn_q(&iadev->tx_return_q));
2850 for (i = 1; i <= iadev->num_rx_desc; i++)
2853 iadev->reass_reg+REASS_MASK_REG);
2854 iadev->rxing = 1;
2861 ia_frontend_intr(iadev);
2885 IADEV *iadev; local
2894 iadev = INPH_IA_DEV(vcc->dev);
2905 if (skb->len > iadev->tx_buf_sz - 8) {
2926 desc = get_desc (iadev, iavcc);
2932 if ((desc == 0) || (desc > iadev->num_tx_desc))
2951 iadev->desc_tbl[desc-1].iavcc = iavcc;
2952 iadev->desc_tbl[desc-1].txskb = skb;
2955 iadev->ffL.tcq_rd += 2;
2956 if (iadev->ffL.tcq_rd > iadev->ffL.tcq_ed)
2957 iadev->ffL.tcq_rd = iadev->ffL.tcq_st;
2958 writew(iadev->ffL.tcq_rd, iadev->seg_reg+TCQ_RD_PTR);
2963 *(u16*)(iadev->seg_ram+iadev->ffL.prq_wr) = desc;
2965 iadev->ffL.prq_wr += 2;
2966 if (iadev->ffL.prq_wr > iadev->ffL.prq_ed)
2967 iadev->ffL.prq_wr = iadev->ffL.prq_st;
2976 trailer = iadev->tx_buf[desc-1].cpcs;
2991 buf_desc_ptr = iadev->seg_ram+TX_DESC_BASE;
2995 writew(TRANSMIT_DONE, iadev->seg_reg+SEG_INTR_STATUS_REG);
3000 clear_lockup (vcc, iadev);
3003 wr_ptr = iadev->tx_dle_q.write;
3005 wr_ptr->sys_pkt_addr = dma_map_single(&iadev->pci->dev, skb->data,
3020 if (++wr_ptr == iadev->tx_dle_q.end)
3021 wr_ptr = iadev->tx_dle_q.start;
3024 wr_ptr->sys_pkt_addr = iadev->tx_buf[desc-1].dma_addr;
3030 wr_ptr->prq_wr_ptr_data = iadev->ffL.prq_wr;
3033 if (++wr_ptr == iadev->tx_dle_q.end)
3034 wr_ptr = iadev->tx_dle_q.start;
3036 iadev->tx_dle_q.write = wr_ptr;
3038 skb_queue_tail(&iadev->tx_dma_q, skb);
3041 iadev->tx_pkt_cnt++;
3043 writel(2, iadev->dma+IPHASE5575_TX_COUNTER);
3066 IADEV *iadev; local
3069 iadev = INPH_IA_DEV(vcc->dev);
3070 if ((!skb)||(skb->len>(iadev->tx_buf_sz-sizeof(struct cpcs_trailer))))
3077 spin_lock_irqsave(&iadev->tx_lock, flags);
3080 spin_unlock_irqrestore(&iadev->tx_lock, flags);
3085 if (skb_peek(&iadev->tx_backlog)) {
3086 skb_queue_tail(&iadev->tx_backlog, skb);
3090 skb_queue_tail(&iadev->tx_backlog, skb);
3093 spin_unlock_irqrestore(&iadev->tx_lock, flags);
3102 IADEV *iadev = INPH_IA_DEV(dev); local
3104 if (iadev->phy_type == FE_25MBIT_PHY) {
3108 if (iadev->phy_type == FE_DS3_PHY)
3110 else if (iadev->phy_type == FE_E3_PHY)
3112 else if (iadev->phy_type == FE_UTP_OPTION)
3117 if (iadev->pci_map_size == 0x40000)
3122 if ((iadev->memType & MEM_SIZE_MASK) == MEM_SIZE_1M)
3124 else if ((iadev->memType & MEM_SIZE_MASK) == MEM_SIZE_512K)
3141 iadev->num_tx_desc, iadev->tx_buf_sz,
3142 iadev->num_rx_desc, iadev->rx_buf_sz,
3143 iadev->rx_pkt_cnt, iadev->tx_pkt_cnt,
3144 iadev->rx_cell_cnt, iadev->tx_cell_cnt,
3145 iadev->drop_rxcell, iadev->drop_rxpkt);
3165 IADEV *iadev; local
3168 iadev = kzalloc(sizeof(*iadev), GFP_KERNEL);
3169 if (!iadev) {
3174 iadev->pci = pdev;
3187 dev->dev_data = iadev;
3190 iadev->LineRate);)
3194 ia_dev[iadev_count] = iadev;
3207 iadev->next_board = ia_boards;
3217 kfree(iadev);
3225 IADEV *iadev = INPH_IA_DEV(dev); local
3236 free_irq(iadev->irq, dev);
3243 iounmap(iadev->base);
3246 ia_free_rx(iadev);
3247 ia_free_tx(iadev);
3249 kfree(iadev);