Lines Matching +full:reg +full:- +full:spacing
29 Complete the ABR logic of the driver, and added the ABR work-
32 Add the flow control logic to the driver to allow rate-limit VC.
72 #define PRIV(dev) ((struct suni_priv *) dev->phy_data)
99 que->next = NULL; in ia_init_rtn_q()
100 que->tail = NULL; in ia_init_rtn_q()
105 data->next = NULL; in ia_enque_head_rtn_q()
106 if (que->next == NULL) in ia_enque_head_rtn_q()
107 que->next = que->tail = data; in ia_enque_head_rtn_q()
109 data->next = que->next; in ia_enque_head_rtn_q()
110 que->next = data; in ia_enque_head_rtn_q()
118 return -ENOMEM; in ia_enque_rtn_q()
119 entry->data = data; in ia_enque_rtn_q()
120 entry->next = NULL; in ia_enque_rtn_q()
121 if (que->next == NULL) in ia_enque_rtn_q()
122 que->next = que->tail = entry; in ia_enque_rtn_q()
124 que->tail->next = entry; in ia_enque_rtn_q()
125 que->tail = que->tail->next; in ia_enque_rtn_q()
132 if (que->next == NULL) in ia_deque_rtn_q()
134 tmpdata = que->next; in ia_deque_rtn_q()
135 if ( que->next == que->tail) in ia_deque_rtn_q()
136 que->next = que->tail = NULL; in ia_deque_rtn_q()
138 que->next = que->next->next; in ia_deque_rtn_q()
148 tcq_wr = readl(dev->seg_reg+TCQ_WR_PTR) & 0xffff; in ia_hack_tcq()
149 while (dev->host_tcq_wr != tcq_wr) { in ia_hack_tcq()
150 desc1 = *(u_short *)(dev->seg_ram + dev->host_tcq_wr); in ia_hack_tcq()
152 else if (!dev->desc_tbl[desc1 -1].timestamp) { in ia_hack_tcq()
153 IF_ABR(printk(" Desc %d is reset at %ld\n", desc1 -1, jiffies);) in ia_hack_tcq()
154 *(u_short *) (dev->seg_ram + dev->host_tcq_wr) = 0; in ia_hack_tcq()
156 else if (dev->desc_tbl[desc1 -1].timestamp) { in ia_hack_tcq()
157 if (!(iavcc_r = dev->desc_tbl[desc1 -1].iavcc)) { in ia_hack_tcq()
161 iavcc_r->vc_desc_cnt--; in ia_hack_tcq()
162 dev->desc_tbl[desc1 -1].timestamp = 0; in ia_hack_tcq()
164 dev->desc_tbl[desc1 -1].txskb, desc1);) in ia_hack_tcq()
165 if (iavcc_r->pcr < dev->rate_limit) { in ia_hack_tcq()
166 IA_SKB_STATE (dev->desc_tbl[desc1-1].txskb) |= IA_TX_DONE; in ia_hack_tcq()
167 if (ia_enque_rtn_q(&dev->tx_return_q, dev->desc_tbl[desc1 -1]) < 0) in ia_hack_tcq()
170 dev->desc_tbl[desc1 -1].iavcc = NULL; in ia_hack_tcq()
171 dev->desc_tbl[desc1 -1].txskb = NULL; in ia_hack_tcq()
173 dev->host_tcq_wr += 2; in ia_hack_tcq()
174 if (dev->host_tcq_wr > dev->ffL.tcq_ed) in ia_hack_tcq()
175 dev->host_tcq_wr = dev->ffL.tcq_st; in ia_hack_tcq()
187 if((time_after(jiffies,timer+50)) || ((dev->ffL.tcq_rd==dev->host_tcq_wr))) { in get_desc()
190 while (i < dev->num_tx_desc) { in get_desc()
191 if (!dev->desc_tbl[i].timestamp) { in get_desc()
195 ltimeout = dev->desc_tbl[i].iavcc->ltimeout; in get_desc()
196 delta = jiffies - dev->desc_tbl[i].timestamp; in get_desc()
198 …IF_ABR(printk("RECOVER run!! desc_tbl %d = %d delta = %ld, time = %ld\n", i,dev->desc_tbl[i].time… in get_desc()
199 if (dev->ffL.tcq_rd == dev->ffL.tcq_st) in get_desc()
200 dev->ffL.tcq_rd = dev->ffL.tcq_ed; in get_desc()
202 dev->ffL.tcq_rd -= 2; in get_desc()
203 *(u_short *)(dev->seg_ram + dev->ffL.tcq_rd) = i+1; in get_desc()
204 if (!dev->desc_tbl[i].txskb || !(iavcc_r = dev->desc_tbl[i].iavcc)) in get_desc()
207 iavcc_r->vc_desc_cnt--; in get_desc()
208 dev->desc_tbl[i].timestamp = 0; in get_desc()
209 dev->desc_tbl[i].iavcc = NULL; in get_desc()
210 dev->desc_tbl[i].txskb = NULL; in get_desc()
215 if (dev->ffL.tcq_rd == dev->host_tcq_wr) in get_desc()
219 desc_num = *(u_short *)(dev->seg_ram + dev->ffL.tcq_rd); in get_desc()
221 while (!desc_num || (dev->desc_tbl[desc_num -1]).timestamp) { in get_desc()
222 dev->ffL.tcq_rd += 2; in get_desc()
223 if (dev->ffL.tcq_rd > dev->ffL.tcq_ed) in get_desc()
224 dev->ffL.tcq_rd = dev->ffL.tcq_st; in get_desc()
225 if (dev->ffL.tcq_rd == dev->host_tcq_wr) in get_desc()
227 desc_num = *(u_short *)(dev->seg_ram + dev->ffL.tcq_rd); in get_desc()
231 dev->desc_tbl[desc_num -1].timestamp = jiffies; in get_desc()
240 struct main_vc *abr_vc = (struct main_vc *)dev->MAIN_VC_TABLE_ADDR; in clear_lockup()
241 struct ext_vc *eabr_vc = (struct ext_vc *)dev->EXT_VC_TABLE_ADDR; in clear_lockup()
244 if (vcc->qos.txtp.traffic_class == ATM_ABR) { in clear_lockup()
245 vcstatus = (vcstatus_t *) &(dev->testTable[vcc->vci]->vc_status); in clear_lockup()
246 vcstatus->cnt++; in clear_lockup()
248 if( vcstatus->cnt == 0x05 ) { in clear_lockup()
249 abr_vc += vcc->vci; in clear_lockup()
250 eabr_vc += vcc->vci; in clear_lockup()
251 if( eabr_vc->last_desc ) { in clear_lockup()
252 if( (abr_vc->status & 0x07) == ABR_STATE /* 0x2 */ ) { in clear_lockup()
255 if ((eabr_vc->last_desc)&&((abr_vc->status & 0x07)==ABR_STATE)) in clear_lockup()
259 tempCellSlot = abr_vc->last_cell_slot; in clear_lockup()
260 tempFract = abr_vc->fraction; in clear_lockup()
261 if((tempCellSlot == dev->testTable[vcc->vci]->lastTime) in clear_lockup()
262 && (tempFract == dev->testTable[vcc->vci]->fract)) in clear_lockup()
264 dev->testTable[vcc->vci]->lastTime = tempCellSlot; in clear_lockup()
265 dev->testTable[vcc->vci]->fract = tempFract; in clear_lockup()
268 vcstatus->cnt = 0; in clear_lockup()
269 } /* vcstatus->cnt */ in clear_lockup()
273 writew(0xFFFD, dev->seg_reg+MODE_REG_0); in clear_lockup()
276 abr_vc->status &= 0xFFF8; in clear_lockup()
277 abr_vc->status |= 0x0001; /* state is idle */ in clear_lockup()
278 shd_tbl = (u_short *)dev->ABR_SCHED_TABLE_ADDR; in clear_lockup()
279 for( i = 0; ((i < dev->num_vc) && (shd_tbl[i])); i++ ); in clear_lockup()
280 if (i < dev->num_vc) in clear_lockup()
281 shd_tbl[i] = vcc->vci; in clear_lockup()
283 IF_ERR(printk("ABR Seg. may not continue on VC %x\n",vcc->vci);) in clear_lockup()
284 writew(T_ONLINE, dev->seg_reg+MODE_REG_0); in clear_lockup()
285 writew(~(TRANSMIT_DONE|TCQ_NOT_EMPTY), dev->seg_reg+SEG_MASK_REG); in clear_lockup()
286 writew(TRANSMIT_DONE, dev->seg_reg+SEG_INTR_STATUS_REG); in clear_lockup()
287 vcstatus->cnt = 0; in clear_lockup()
296 ** Conversion of 24-bit cellrate (cells/sec) to 16-bit floating point format.
298 ** +----+----+------------------+-------------------------------+
299 ** | R | NZ | 5-bit exponent | 9-bit mantissa |
300 ** +----+----+------------------+-------------------------------+
328 flot = NZ | (i << M_BITS) | ((cr << (M_BITS - i)) & M_MASK); in cellrate_to_float()
330 flot = NZ | (i << M_BITS) | ((cr >> (i - M_BITS)) & M_MASK); in cellrate_to_float()
336 ** Conversion of 16-bit floating point format to 24-bit cellrate (cells/sec).
352 cps <<= (exp - M_BITS);
354 cps >>= (M_BITS - exp);
360 srv_p->class_type = ATM_ABR; in init_abr_vc()
361 srv_p->pcr = dev->LineRate; in init_abr_vc()
362 srv_p->mcr = 0; in init_abr_vc()
363 srv_p->icr = 0x055cb7; in init_abr_vc()
364 srv_p->tbe = 0xffffff; in init_abr_vc()
365 srv_p->frtt = 0x3a; in init_abr_vc()
366 srv_p->rif = 0xf; in init_abr_vc()
367 srv_p->rdf = 0xb; in init_abr_vc()
368 srv_p->nrm = 0x4; in init_abr_vc()
369 srv_p->trm = 0x7; in init_abr_vc()
370 srv_p->cdf = 0x3; in init_abr_vc()
371 srv_p->adtf = 50; in init_abr_vc()
383 f_abr_vc =(f_vc_abr_entry *)dev->MAIN_VC_TABLE_ADDR; in ia_open_abr_vc()
384 f_abr_vc += vcc->vci; in ia_open_abr_vc()
388 if (srv_p->pcr == 0) in ia_open_abr_vc()
390 if (srv_p->pcr > dev->LineRate) in ia_open_abr_vc()
391 srv_p->pcr = dev->LineRate; in ia_open_abr_vc()
392 if ((srv_p->mcr + dev->sum_mcr) > dev->LineRate) in ia_open_abr_vc()
394 if (srv_p->mcr > srv_p->pcr) in ia_open_abr_vc()
396 if (!(srv_p->icr)) in ia_open_abr_vc()
397 srv_p->icr = srv_p->pcr; in ia_open_abr_vc()
398 if ((srv_p->icr < srv_p->mcr) || (srv_p->icr > srv_p->pcr)) in ia_open_abr_vc()
400 if ((srv_p->tbe < MIN_TBE) || (srv_p->tbe > MAX_TBE)) in ia_open_abr_vc()
402 if ((srv_p->frtt < MIN_FRTT) || (srv_p->frtt > MAX_FRTT)) in ia_open_abr_vc()
404 if (srv_p->nrm > MAX_NRM) in ia_open_abr_vc()
406 if (srv_p->trm > MAX_TRM) in ia_open_abr_vc()
408 if (srv_p->adtf > MAX_ADTF) in ia_open_abr_vc()
410 else if (srv_p->adtf == 0) in ia_open_abr_vc()
411 srv_p->adtf = 1; in ia_open_abr_vc()
412 if (srv_p->cdf > MAX_CDF) in ia_open_abr_vc()
414 if (srv_p->rif > MAX_RIF) in ia_open_abr_vc()
416 if (srv_p->rdf > MAX_RDF) in ia_open_abr_vc()
420 f_abr_vc->f_vc_type = ABR; in ia_open_abr_vc()
421 nrm = 2 << srv_p->nrm; /* (2 ** (srv_p->nrm +1)) */ in ia_open_abr_vc()
422 /* i.e 2**n = 2 << (n-1) */ in ia_open_abr_vc()
423 f_abr_vc->f_nrm = nrm << 8 | nrm; in ia_open_abr_vc()
424 trm = 100000/(2 << (16 - srv_p->trm)); in ia_open_abr_vc()
426 f_abr_vc->f_nrmexp =(((srv_p->nrm +1) & 0x0f) << 12)|(MRM << 8) | trm; in ia_open_abr_vc()
427 crm = srv_p->tbe / nrm; in ia_open_abr_vc()
429 f_abr_vc->f_crm = crm & 0xff; in ia_open_abr_vc()
430 f_abr_vc->f_pcr = cellrate_to_float(srv_p->pcr); in ia_open_abr_vc()
431 icr = min( srv_p->icr, (srv_p->tbe > srv_p->frtt) ? in ia_open_abr_vc()
432 ((srv_p->tbe/srv_p->frtt)*1000000) : in ia_open_abr_vc()
433 (1000000/(srv_p->frtt/srv_p->tbe))); in ia_open_abr_vc()
434 f_abr_vc->f_icr = cellrate_to_float(icr); in ia_open_abr_vc()
435 adtf = (10000 * srv_p->adtf)/8192; in ia_open_abr_vc()
437 f_abr_vc->f_cdf = ((7 - srv_p->cdf) << 12 | adtf) & 0xfff; in ia_open_abr_vc()
438 f_abr_vc->f_mcr = cellrate_to_float(srv_p->mcr); in ia_open_abr_vc()
439 f_abr_vc->f_acr = f_abr_vc->f_icr; in ia_open_abr_vc()
440 f_abr_vc->f_status = 0x0042; in ia_open_abr_vc()
443 ptr16 = (u_short *)(dev->reass_ram + REASS_TABLE*dev->memSize); in ia_open_abr_vc()
444 *(ptr16 + vcc->vci) = NO_AAL5_PKT | REASS_ABR; in ia_open_abr_vc()
445 r_abr_vc = (r_vc_abr_entry*)(dev->reass_ram+ABR_VC_TABLE*dev->memSize); in ia_open_abr_vc()
446 r_abr_vc += vcc->vci; in ia_open_abr_vc()
447 r_abr_vc->r_status_rdf = (15 - srv_p->rdf) & 0x000f; in ia_open_abr_vc()
448 air = srv_p->pcr << (15 - srv_p->rif); in ia_open_abr_vc()
450 r_abr_vc->r_air = cellrate_to_float(air); in ia_open_abr_vc()
451 dev->testTable[vcc->vci]->vc_status = VC_ACTIVE | VC_ABR; in ia_open_abr_vc()
452 dev->sum_mcr += srv_p->mcr; in ia_open_abr_vc()
453 dev->n_abr++; in ia_open_abr_vc()
466 u32 spacing; in ia_cbr_setup() local
474 if (vcc->qos.txtp.max_pcr <= 0) { in ia_cbr_setup()
476 return -1; in ia_cbr_setup()
478 rate = vcc->qos.txtp.max_pcr; in ia_cbr_setup()
479 entries = rate / dev->Granularity; in ia_cbr_setup()
481 entries, rate, dev->Granularity);) in ia_cbr_setup()
484 rateLow = entries * dev->Granularity; in ia_cbr_setup()
485 rateHigh = (entries + 1) * dev->Granularity; in ia_cbr_setup()
486 if (3*(rate - rateLow) > (rateHigh - rate)) in ia_cbr_setup()
488 if (entries > dev->CbrRemEntries) { in ia_cbr_setup()
491 entries, dev->CbrRemEntries);) in ia_cbr_setup()
492 return -EBUSY; in ia_cbr_setup()
496 ia_vcc->NumCbrEntry = entries; in ia_cbr_setup()
497 dev->sum_mcr += entries * dev->Granularity; in ia_cbr_setup()
502 spacing = dev->CbrTotEntries / entries; in ia_cbr_setup()
503 sp_mod = dev->CbrTotEntries % entries; // get modulo in ia_cbr_setup()
506 vcIndex = vcc->vci; in ia_cbr_setup()
507 IF_CBR(printk("Vci=0x%x,Spacing=0x%x,Sp_mod=0x%x\n",vcIndex,spacing,sp_mod);) in ia_cbr_setup()
514 idealSlot = dev->CbrEntryPt; in ia_cbr_setup()
515 dev->CbrEntryPt += 2; // Adding 2 helps to prevent clumping in ia_cbr_setup()
516 if (dev->CbrEntryPt >= dev->CbrTotEntries) in ia_cbr_setup()
517 dev->CbrEntryPt -= dev->CbrTotEntries;// Wrap if necessary in ia_cbr_setup()
519 idealSlot += (u32)(spacing + fracSlot); // Point to the next location in ia_cbr_setup()
524 if (idealSlot >= (int)dev->CbrTotEntries) in ia_cbr_setup()
525 idealSlot -= dev->CbrTotEntries; in ia_cbr_setup()
528 SchedTbl = (u16*)(dev->seg_ram+CBR_SCHED_TABLE*dev->memSize); in ia_cbr_setup()
538 testSlot = idealSlot - inc; in ia_cbr_setup()
540 testSlot += dev->CbrTotEntries; in ia_cbr_setup()
549 if (testSlot >= (int)dev->CbrTotEntries) { // Wrap if necessary in ia_cbr_setup()
550 testSlot -= dev->CbrTotEntries; in ia_cbr_setup()
551 IF_CBR(printk("TotCbrEntries=%d",dev->CbrTotEntries);) in ia_cbr_setup()
563 dev->CbrRemEntries--; in ia_cbr_setup()
564 toBeAssigned--; in ia_cbr_setup()
568 dev->NumEnabledCBR++; in ia_cbr_setup()
569 if (dev->NumEnabledCBR == 1) { in ia_cbr_setup()
570 writew((CBR_EN | UBR_EN | ABR_EN | (0x23 << 2)), dev->seg_reg+STPARMS); in ia_cbr_setup()
580 iadev = INPH_IA_DEV(vcc->dev); in ia_cbrVc_close()
581 iadev->NumEnabledCBR--; in ia_cbrVc_close()
582 SchedTbl = (u16*)(iadev->seg_ram+CBR_SCHED_TABLE*iadev->memSize); in ia_cbrVc_close()
583 if (iadev->NumEnabledCBR == 0) { in ia_cbrVc_close()
584 writew((UBR_EN | ABR_EN | (0x23 << 2)), iadev->seg_reg+STPARMS); in ia_cbrVc_close()
588 for (i=0; i < iadev->CbrTotEntries; i++) in ia_cbrVc_close()
590 if (*SchedTbl == vcc->vci) { in ia_cbrVc_close()
591 iadev->CbrRemEntries++; in ia_cbrVc_close()
603 if (iadev->host_tcq_wr >= iadev->ffL.tcq_rd) in ia_avail_descs()
604 tmp = (iadev->host_tcq_wr - iadev->ffL.tcq_rd) / 2; in ia_avail_descs()
606 tmp = (iadev->ffL.tcq_ed - iadev->ffL.tcq_rd + 2 + iadev->host_tcq_wr - in ia_avail_descs()
607 iadev->ffL.tcq_st) / 2; in ia_avail_descs()
619 while (num_desc && (skb = skb_dequeue(&iadev->tx_backlog))) { in ia_que_tx()
620 if (!(vcc = ATM_SKB(skb)->vcc)) { in ia_que_tx()
625 if (!test_bit(ATM_VF_READY,&vcc->flags)) { in ia_que_tx()
627 printk("Free the SKB on closed vci %d \n", vcc->vci); in ia_que_tx()
631 skb_queue_head(&iadev->tx_backlog, skb); in ia_que_tx()
633 num_desc--; in ia_que_tx()
645 while ( (rtne = ia_deque_rtn_q(&iadev->tx_return_q))) { in ia_tx_poll()
646 skb = rtne->data.txskb; in ia_tx_poll()
651 vcc = ATM_SKB(skb)->vcc; in ia_tx_poll()
665 skb1 = skb_dequeue(&iavcc->txing_skb); in ia_tx_poll()
668 printk("IA_tx_intr: Vci %d lost pkt!!!\n", vcc->vci); in ia_tx_poll()
671 if ((vcc->pop) && (skb1->len != 0)) in ia_tx_poll()
673 vcc->pop(vcc, skb1); in ia_tx_poll()
674 IF_EVENT(printk("Transmit Done - skb 0x%lx return\n", in ia_tx_poll()
679 skb1 = skb_dequeue(&iavcc->txing_skb); in ia_tx_poll()
682 IF_EVENT(printk("IA: Vci %d - skb not found requeued\n",vcc->vci);) in ia_tx_poll()
683 ia_enque_head_rtn_q (&iadev->tx_return_q, rtne); in ia_tx_poll()
686 if ((vcc->pop) && (skb->len != 0)) in ia_tx_poll()
688 vcc->pop(vcc, skb); in ia_tx_poll()
689 IF_EVENT(printk("Tx Done - skb 0x%lx return\n",(long)skb);) in ia_tx_poll()
716 for (i=15; i>=0; i--) {
722 t = readl(iadev->reg+IPHASE5575_EEPROM_ACCESS);
724 t = readl(iadev->reg+IPHASE5575_EEPROM_ACCESS);
751 for (i=15; i>=0; i--) { in ia_eeprom_get()
762 iadev->memType = memType;
764 iadev->num_tx_desc = IA_TX_BUF;
765 iadev->tx_buf_sz = IA_TX_BUF_SZ;
766 iadev->num_rx_desc = IA_RX_BUF;
767 iadev->rx_buf_sz = IA_RX_BUF_SZ;
770 iadev->num_tx_desc = IA_TX_BUF / 2;
772 iadev->num_tx_desc = IA_TX_BUF;
773 iadev->tx_buf_sz = IA_TX_BUF_SZ;
775 iadev->num_rx_desc = IA_RX_BUF / 2;
777 iadev->num_rx_desc = IA_RX_BUF;
778 iadev->rx_buf_sz = IA_RX_BUF_SZ;
782 iadev->num_tx_desc = IA_TX_BUF / 8;
784 iadev->num_tx_desc = IA_TX_BUF;
785 iadev->tx_buf_sz = IA_TX_BUF_SZ;
787 iadev->num_rx_desc = IA_RX_BUF / 8;
789 iadev->num_rx_desc = IA_RX_BUF;
790 iadev->rx_buf_sz = IA_RX_BUF_SZ;
792 iadev->rx_pkt_ram = TX_PACKET_RAM + (iadev->num_tx_desc * iadev->tx_buf_sz);
794 iadev->num_tx_desc, iadev->tx_buf_sz, iadev->num_rx_desc,
795 iadev->rx_buf_sz, iadev->rx_pkt_ram);)
799 iadev->phy_type = PHY_OC3C_S;
801 iadev->phy_type = PHY_UTP155;
803 iadev->phy_type = PHY_OC3C_M;
806 iadev->phy_type = memType & FE_MASK;
807 IF_INIT(printk("memType = 0x%x iadev->phy_type = 0x%x\n",
808 memType,iadev->phy_type);)
809 if (iadev->phy_type == FE_25MBIT_PHY)
810 iadev->LineRate = (u32)(((25600000/8)*26)/(27*53));
811 else if (iadev->phy_type == FE_DS3_PHY)
812 iadev->LineRate = (u32)(((44736000/8)*26)/(27*53));
813 else if (iadev->phy_type == FE_E3_PHY)
814 iadev->LineRate = (u32)(((34368000/8)*26)/(27*53));
816 iadev->LineRate = (u32)(ATM_OC3_PCR);
817 IF_INIT(printk("iadev->LineRate = %d \n", iadev->LineRate);)
821 static u32 ia_phy_read32(struct iadev_priv *ia, unsigned int reg) argument
823 return readl(ia->phy + (reg >> 2));
826 static void ia_phy_write32(struct iadev_priv *ia, unsigned int reg, u32 val) argument
828 writel(val, ia->phy + (reg >> 2));
835 if (iadev->phy_type & FE_25MBIT_PHY) {
837 iadev->carrier_detect = (status & MB25_IS_GSB) ? 1 : 0;
838 } else if (iadev->phy_type & FE_DS3_PHY) {
841 iadev->carrier_detect = (status & SUNI_DS3_LOSV) ? 0 : 1;
842 } else if (iadev->phy_type & FE_E3_PHY) {
845 iadev->carrier_detect = (status & SUNI_E3_LOS) ? 0 : 1;
848 iadev->carrier_detect = (status & SUNI_LOSV) ? 0 : 1;
852 iadev->carrier_detect ? "detected" : "lost signal");
858 mb25->mb25_master_ctrl = MB25_MC_DRIC | MB25_MC_DREC | MB25_MC_ENABLED;
863 iadev->carrier_detect =
868 u16 reg; member
875 while (len--) {
876 ia_phy_write32(iadev, regs->reg, regs->val);
894 iadev->carrier_detect = (status & SUNI_DS3_LOSV) ? 0 : 1;
915 iadev->carrier_detect = (status & SUNI_E3_LOS) ? 0 : 1;
957 if (iadev->phy_type & FE_DS3_PHY)
968 suni_pm7345->suni_rxcp_intr_en_sts |= SUNI_OOCDE;
1017 RAM_BASE*((iadev->mem)/(128 * 1024))
1019 IPHASE5575_FRAG_CONTROL_RAM_BASE*((iadev->mem)/(128 * 1024))
1021 IPHASE5575_REASS_CONTROL_RAM_BASE*((iadev->mem)/(128 * 1024))
1024 /*-- some utilities and memory allocation stuff will come here -------------*/
1031 // regval = readl((u32)ia_cmds->maddr);
1032 tcq_wr_ptr = readw(iadev->seg_reg+TCQ_WR_PTR);
1034 tcq_wr_ptr, readw(iadev->seg_ram+tcq_wr_ptr),
1035 readw(iadev->seg_ram+tcq_wr_ptr-2));
1036 printk(" host_tcq_wr = 0x%x host_tcq_rd = 0x%x \n", iadev->host_tcq_wr,
1037 iadev->ffL.tcq_rd);
1038 tcq_st_ptr = readw(iadev->seg_reg+TCQ_ST_ADR);
1039 tcq_ed_ptr = readw(iadev->seg_reg+TCQ_ED_ADR);
1043 tmp = iadev->seg_ram+tcq_st_ptr;
1047 for(i=0; i <iadev->num_tx_desc; i++)
1048 printk("Desc_tbl[%d] = %d \n", i, iadev->desc_tbl[i].timestamp);
1052 /*----------------------------- Receiving side stuff --------------------------*/
1063 state = readl(iadev->reass_reg + STATE_REG) & 0xffff;
1066 excpq_rd_ptr = readw(iadev->reass_reg + EXCP_Q_RD_PTR) & 0xffff;
1068 if (excpq_rd_ptr == *(u16*)(iadev->reass_reg + EXCP_Q_WR_PTR))
1071 vci = readw(iadev->reass_ram+excpq_rd_ptr);
1072 error = readw(iadev->reass_ram+excpq_rd_ptr+2) & 0x0007;
1075 if (excpq_rd_ptr > (readw(iadev->reass_reg + EXCP_Q_ED_ADR)& 0xffff))
1076 excpq_rd_ptr = readw(iadev->reass_reg + EXCP_Q_ST_ADR)& 0xffff;
1077 writew( excpq_rd_ptr, iadev->reass_reg + EXCP_Q_RD_PTR);
1078 state = readl(iadev->reass_reg + STATE_REG) & 0xffff;
1087 writew(desc, iadev->reass_ram+iadev->rfL.fdq_wr);
1088 iadev->rfL.fdq_wr +=2;
1089 if (iadev->rfL.fdq_wr > iadev->rfL.fdq_ed)
1090 iadev->rfL.fdq_wr = iadev->rfL.fdq_st;
1091 writew(iadev->rfL.fdq_wr, iadev->reass_reg+FREEQ_WR_PTR);
1108 if (iadev->rfL.pcq_rd == (readw(iadev->reass_reg+PCQ_WR_PTR)&0xffff))
1110 printk(KERN_ERR DEV_LABEL "(itf %d) Receive queue empty\n", dev->number);
1111 return -EINVAL;
1114 desc = readw(iadev->reass_ram+iadev->rfL.pcq_rd) & 0x1fff;
1115 IF_RX(printk("reass_ram = %p iadev->rfL.pcq_rd = 0x%x desc = %d\n",
1116 iadev->reass_ram, iadev->rfL.pcq_rd, desc);
1118 readw(iadev->reass_reg+PCQ_WR_PTR)&0xffff);)
1119 /* update the read pointer - maybe we shud do this in the end*/
1120 if ( iadev->rfL.pcq_rd== iadev->rfL.pcq_ed)
1121 iadev->rfL.pcq_rd = iadev->rfL.pcq_st;
1123 iadev->rfL.pcq_rd += 2;
1124 writew(iadev->rfL.pcq_rd, iadev->reass_reg+PCQ_RD_PTR);
1127 update stuff. - doesn't seem to be any update necessary
1129 buf_desc_ptr = iadev->RX_DESC_BASE_ADDR;
1132 if (!desc || (desc > iadev->num_rx_desc) ||
1133 ((buf_desc_ptr->vc_index & 0xffff) >= iadev->num_vc)) {
1136 return -1;
1138 vcc = iadev->rx_open[buf_desc_ptr->vc_index & 0xffff];
1143 return -1;
1148 status = (u_short) (buf_desc_ptr->desc_mode);
1151 atomic_inc(&vcc->stats->rx_err);
1169 buf_addr = (buf_desc_ptr->buf_start_hi << 16) | buf_desc_ptr->buf_start_lo;
1170 dma_addr = (buf_desc_ptr->dma_start_hi << 16) | buf_desc_ptr->dma_start_lo;
1171 len = dma_addr - buf_addr;
1172 if (len > iadev->rx_buf_sz) {
1173 printk("Over %d bytes sdu received, dropped!!!\n", iadev->rx_buf_sz);
1174 atomic_inc(&vcc->stats->rx_err);
1179 if (vcc->vci < 32)
1185 ATM_SKB(skb)->vcc = vcc;
1187 skb_queue_tail(&iadev->rx_dma_q, skb);
1190 wr_ptr = iadev->rx_dle_q.write;
1191 wr_ptr->sys_pkt_addr = dma_map_single(&iadev->pci->dev, skb->data,
1193 wr_ptr->local_pkt_addr = buf_addr;
1194 wr_ptr->bytes = len; /* We don't know this do we ?? */
1195 wr_ptr->mode = DMA_INT_ENABLE;
1198 if(++wr_ptr == iadev->rx_dle_q.end)
1199 wr_ptr = iadev->rx_dle_q.start;
1200 iadev->rx_dle_q.write = wr_ptr;
1203 writel(1, iadev->dma+IPHASE5575_RX_COUNTER);
1217 status = readl(iadev->reass_reg+REASS_INTR_STATUS_REG) & 0xffff;
1227 state = readl(iadev->reass_reg + STATE_REG) & 0xffff;
1232 state = readl(iadev->reass_reg + STATE_REG) & 0xffff;
1234 iadev->rxing = 1;
1238 if (iadev->rxing) {
1239 iadev->rx_tmp_cnt = iadev->rx_pkt_cnt;
1240 iadev->rx_tmp_jif = jiffies;
1241 iadev->rxing = 0;
1243 else if ((time_after(jiffies, iadev->rx_tmp_jif + 50)) &&
1244 ((iadev->rx_pkt_cnt - iadev->rx_tmp_cnt) == 0)) {
1245 for (i = 1; i <= iadev->num_rx_desc; i++)
1248 writew( ~(RX_FREEQ_EMPT|RX_EXCP_RCVD),iadev->reass_reg+REASS_MASK_REG);
1249 iadev->rxing = 1;
1285 - do we really need to do this. Think not. */
1289 dle = iadev->rx_dle_q.read;
1290 dle_lp = readl(iadev->dma+IPHASE5575_RX_LIST_ADDR) & (sizeof(struct dle)*DLE_ENTRIES - 1);
1291 cur_dle = (struct dle*)(iadev->rx_dle_q.start + (dle_lp >> 4));
1295 skb = skb_dequeue(&iadev->rx_dma_q);
1301 if (!(len = skb->len))
1312 dma_unmap_single(&iadev->pci->dev, iadev->rx_dle_q.write->sys_pkt_addr,
1315 vcc = ATM_SKB(skb)->vcc;
1324 atomic_inc(&vcc->stats->rx_err);
1325 atm_return(vcc, skb->truesize);
1330 trailer = (struct cpcs_trailer*)((u_char *)skb->data +
1331 skb->len - sizeof(*trailer));
1332 length = swap_byte_order(trailer->length);
1333 if ((length > iadev->rx_buf_sz) || (length >
1334 (skb->len - sizeof(struct cpcs_trailer))))
1336 atomic_inc(&vcc->stats->rx_err);
1338 length, skb->len);)
1339 atm_return(vcc, skb->truesize);
1346 IF_RXPKT(printk("\nDmad Recvd data: len = %d \n", skb->len);
1347 xdump(skb->data, skb->len, "RX: ");
1351 vcc->push(vcc,skb);
1352 atomic_inc(&vcc->stats->rx);
1353 iadev->rx_pkt_cnt++;
1356 if (++dle == iadev->rx_dle_q.end)
1357 dle = iadev->rx_dle_q.start;
1359 iadev->rx_dle_q.read = dle;
1363 if (!iadev->rxing) {
1364 state = readl(iadev->reass_reg + STATE_REG) & 0xffff;
1366 state = readl(iadev->reass_reg + REASS_MASK_REG) & 0xffff;
1368 iadev->reass_reg+REASS_MASK_REG);
1369 iadev->rxing++;
1380 IF_EVENT(printk("iadev: open_rx %d.%d\n", vcc->vpi, vcc->vci);)
1382 if (vcc->qos.rxtp.traffic_class == ATM_NONE) return 0;
1383 iadev = INPH_IA_DEV(vcc->dev);
1384 if (vcc->qos.rxtp.traffic_class == ATM_ABR) {
1385 if (iadev->phy_type & FE_25MBIT_PHY) {
1387 return -EINVAL;
1392 vc_table = iadev->reass_ram+RX_VC_TABLE*iadev->memSize;
1393 vc_table += vcc->vci;
1396 *vc_table = vcc->vci << 6;
1399 if ((vcc->qos.rxtp.traffic_class == ATM_ABR) ||
1400 (vcc->qos.txtp.traffic_class == ATM_ABR))
1407 reass_ptr = iadev->reass_ram+REASS_TABLE*iadev->memSize;
1408 reass_ptr += vcc->vci;
1412 if (iadev->rx_open[vcc->vci])
1414 vcc->dev->number, vcc->vci);
1415 iadev->rx_open[vcc->vci] = vcc;
1433 // spin_lock_init(&iadev->rx_lock);
1435 /* Allocate 4k bytes - more aligned than needed (4k boundary) */
1436 dle_addr = dma_alloc_coherent(&iadev->pci->dev, DLE_TOTAL_SIZE,
1437 &iadev->rx_dle_dma, GFP_KERNEL);
1442 iadev->rx_dle_q.start = (struct dle *)dle_addr;
1443 iadev->rx_dle_q.read = iadev->rx_dle_q.start;
1444 iadev->rx_dle_q.write = iadev->rx_dle_q.start;
1445 iadev->rx_dle_q.end = (struct dle*)((unsigned long)dle_addr+sizeof(struct dle)*DLE_ENTRIES);
1451 writel(iadev->rx_dle_dma & 0xfffff000,
1452 iadev->dma + IPHASE5575_RX_LIST_ADDR);
1454 iadev->dma+IPHASE5575_TX_LIST_ADDR,
1455 readl(iadev->dma + IPHASE5575_TX_LIST_ADDR));
1457 iadev->dma+IPHASE5575_RX_LIST_ADDR,
1458 readl(iadev->dma + IPHASE5575_RX_LIST_ADDR));)
1460 writew(0xffff, iadev->reass_reg+REASS_MASK_REG);
1461 writew(0, iadev->reass_reg+MODE_REG);
1462 writew(RESET_REASS, iadev->reass_reg+REASS_COMMAND_REG);
1465 -------------------------------
1467 Buffer descr 0x0000 (736 - 23K)
1468 VP Table 0x5c00 (256 - 512)
1469 Except q 0x5e00 (128 - 512)
1470 Free buffer q 0x6000 (1K - 2K)
1471 Packet comp q 0x6800 (1K - 2K)
1472 Reass Table 0x7000 (1K - 2K)
1473 VC Table 0x7800 (1K - 2K)
1474 ABR VC Table 0x8000 (1K - 32K)
1478 writew(RX_DESC_BASE >> 16, iadev->reass_reg+REASS_DESC_BASE);
1480 writew(iadev->rx_buf_sz, iadev->reass_reg+BUF_SIZE);
1483 iadev->RX_DESC_BASE_ADDR = iadev->reass_ram+RX_DESC_BASE*iadev->memSize;
1484 buf_desc_ptr = iadev->RX_DESC_BASE_ADDR;
1487 rx_pkt_start = iadev->rx_pkt_ram;
1488 for(i=1; i<=iadev->num_rx_desc; i++)
1491 buf_desc_ptr->buf_start_hi = rx_pkt_start >> 16;
1492 buf_desc_ptr->buf_start_lo = rx_pkt_start & 0x0000ffff;
1494 rx_pkt_start += iadev->rx_buf_sz;
1497 i = FREE_BUF_DESC_Q*iadev->memSize;
1498 writew(i >> 16, iadev->reass_reg+REASS_QUEUE_BASE);
1499 writew(i, iadev->reass_reg+FREEQ_ST_ADR);
1500 writew(i+iadev->num_rx_desc*sizeof(u_short),
1501 iadev->reass_reg+FREEQ_ED_ADR);
1502 writew(i, iadev->reass_reg+FREEQ_RD_PTR);
1503 writew(i+iadev->num_rx_desc*sizeof(u_short),
1504 iadev->reass_reg+FREEQ_WR_PTR);
1506 freeq_st_adr = readw(iadev->reass_reg+FREEQ_ST_ADR);
1507 freeq_start = (u_short *)(iadev->reass_ram+freeq_st_adr);
1508 for(i=1; i<=iadev->num_rx_desc; i++)
1515 i = (PKT_COMP_Q * iadev->memSize) & 0xffff;
1516 writew(i, iadev->reass_reg+PCQ_ST_ADR);
1517 writew(i+iadev->num_vc*sizeof(u_short), iadev->reass_reg+PCQ_ED_ADR);
1518 writew(i, iadev->reass_reg+PCQ_RD_PTR);
1519 writew(i, iadev->reass_reg+PCQ_WR_PTR);
1522 i = (EXCEPTION_Q * iadev->memSize) & 0xffff;
1523 writew(i, iadev->reass_reg+EXCP_Q_ST_ADR);
1525 iadev->reass_reg+EXCP_Q_ED_ADR);
1526 writew(i, iadev->reass_reg+EXCP_Q_RD_PTR);
1527 writew(i, iadev->reass_reg+EXCP_Q_WR_PTR);
1530 iadev->rfL.fdq_st = readw(iadev->reass_reg+FREEQ_ST_ADR) & 0xffff;
1531 iadev->rfL.fdq_ed = readw(iadev->reass_reg+FREEQ_ED_ADR) & 0xffff ;
1532 iadev->rfL.fdq_rd = readw(iadev->reass_reg+FREEQ_RD_PTR) & 0xffff;
1533 iadev->rfL.fdq_wr = readw(iadev->reass_reg+FREEQ_WR_PTR) & 0xffff;
1534 iadev->rfL.pcq_st = readw(iadev->reass_reg+PCQ_ST_ADR) & 0xffff;
1535 iadev->rfL.pcq_ed = readw(iadev->reass_reg+PCQ_ED_ADR) & 0xffff;
1536 iadev->rfL.pcq_rd = readw(iadev->reass_reg+PCQ_RD_PTR) & 0xffff;
1537 iadev->rfL.pcq_wr = readw(iadev->reass_reg+PCQ_WR_PTR) & 0xffff;
1540 iadev->rfL.pcq_st, iadev->rfL.pcq_ed, iadev->rfL.pcq_rd,
1541 iadev->rfL.pcq_wr);)
1542 /* just for check - no VP TBL */
1544 /* writew(0x0b80, iadev->reass_reg+VP_LKUP_BASE); */
1546 - I guess we can write all 1s or 0x000f in the entire memory
1551 i = REASS_TABLE * iadev->memSize;
1552 writew((i >> 3), iadev->reass_reg+REASS_TABLE_BASE);
1554 reass_table = (u16 *)(iadev->reass_ram+i);
1555 j = REASS_TABLE_SZ * iadev->memSize;
1560 while (i != iadev->num_vc) {
1564 i = RX_VC_TABLE * iadev->memSize;
1565 writew(((i>>3) & 0xfff8) | vcsize_sel, iadev->reass_reg+VC_LKUP_BASE);
1566 vc_table = (u16 *)(iadev->reass_ram+RX_VC_TABLE*iadev->memSize);
1567 j = RX_VC_TABLE_SZ * iadev->memSize;
1579 i = ABR_VC_TABLE * iadev->memSize;
1580 writew(i >> 3, iadev->reass_reg+ABR_LKUP_BASE);
1582 i = ABR_VC_TABLE * iadev->memSize;
1583 abr_vc_table = (struct abr_vc_table *)(iadev->reass_ram+i);
1584 j = REASS_TABLE_SZ * iadev->memSize;
1587 abr_vc_table->rdf = 0x0003;
1588 abr_vc_table->air = 0x5eb1;
1595 writew(0xff00, iadev->reass_reg+VP_FILTER);
1596 writew(0, iadev->reass_reg+XTRA_RM_OFFSET);
1597 writew(0x1, iadev->reass_reg+PROTOCOL_ID);
1603 writew(0xF6F8, iadev->reass_reg+PKT_TM_CNT );
1606 j += 2 * (j - 1);
1608 writew(i, iadev->reass_reg+TMOUT_RANGE);
1611 for(i=0; i<iadev->num_tx_desc;i++)
1612 iadev->desc_tbl[i].timestamp = 0;
1614 /* to clear the interrupt status register - read it */
1615 readw(iadev->reass_reg+REASS_INTR_STATUS_REG);
1617 /* Mask Register - clear it */
1618 writew(~(RX_FREEQ_EMPT|RX_PKT_RCVD), iadev->reass_reg+REASS_MASK_REG);
1620 skb_queue_head_init(&iadev->rx_dma_q);
1621 iadev->rx_free_desc_qhead = NULL;
1623 iadev->rx_open = kcalloc(iadev->num_vc, sizeof(void *), GFP_KERNEL);
1624 if (!iadev->rx_open) {
1626 dev->number);
1630 iadev->rxing = 1;
1631 iadev->rx_pkt_cnt = 0;
1633 writew(R_ONLINE, iadev->reass_reg+MODE_REG);
1637 dma_free_coherent(&iadev->pci->dev, DLE_TOTAL_SIZE, iadev->rx_dle_q.start,
1638 iadev->rx_dle_dma);
1640 return -ENOMEM;
1648 Buffer descr 0x0000 (128 - 4K)
1649 UBR sched 0x1000 (1K - 4K)
1650 UBR Wait q 0x2000 (1K - 4K)
1652 (128 - 256) each
1653 extended VC 0x4000 (1K - 8K)
1654 ABR sched 0x6000 and ABR wait queue (1K - 2K) each
1656 VC table 0x8000 (1K - 32K)
1667 status = readl(iadev->seg_reg+SEG_INTR_STATUS_REG);
1671 spin_lock_irqsave(&iadev->tx_lock, flags);
1673 spin_unlock_irqrestore(&iadev->tx_lock, flags);
1674 writew(TRANSMIT_DONE, iadev->seg_reg+SEG_INTR_STATUS_REG);
1675 if (iadev->close_pending)
1676 wake_up(&iadev->close_wait);
1695 spin_lock_irqsave(&iadev->tx_lock, flags);
1696 dle = iadev->tx_dle_q.read;
1697 dle_lp = readl(iadev->dma+IPHASE5575_TX_LIST_ADDR) &
1698 (sizeof(struct dle)*DLE_ENTRIES - 1);
1699 cur_dle = (struct dle*)(iadev->tx_dle_q.start + (dle_lp >> 4));
1703 skb = skb_dequeue(&iadev->tx_dma_q);
1707 if (!((dle - iadev->tx_dle_q.start)%(2*sizeof(struct dle)))) {
1708 dma_unmap_single(&iadev->pci->dev, dle->sys_pkt_addr, skb->len,
1711 vcc = ATM_SKB(skb)->vcc;
1714 spin_unlock_irqrestore(&iadev->tx_lock, flags);
1722 spin_unlock_irqrestore(&iadev->tx_lock, flags);
1726 if (vcc->qos.txtp.pcr >= iadev->rate_limit) {
1727 if ((vcc->pop) && (skb->len != 0))
1729 vcc->pop(vcc, skb);
1735 else { /* Hold the rate-limited skb for flow control */
1737 skb_queue_tail(&iavcc->txing_skb, skb);
1740 if (++dle == iadev->tx_dle_q.end)
1741 dle = iadev->tx_dle_q.start;
1743 iadev->tx_dle_q.read = dle;
1744 spin_unlock_irqrestore(&iadev->tx_lock, flags);
1754 IF_EVENT(printk("iadev: open_tx entered vcc->vci = %d\n", vcc->vci);)
1755 if (vcc->qos.txtp.traffic_class == ATM_NONE) return 0;
1756 iadev = INPH_IA_DEV(vcc->dev);
1758 if (iadev->phy_type & FE_25MBIT_PHY) {
1759 if (vcc->qos.txtp.traffic_class == ATM_ABR) {
1761 return -EINVAL;
1763 if (vcc->qos.txtp.traffic_class == ATM_CBR) {
1765 return -EINVAL;
1770 if (vcc->qos.txtp.max_sdu >
1771 (iadev->tx_buf_sz - sizeof(struct cpcs_trailer))){
1773 vcc->qos.txtp.max_sdu,iadev->tx_buf_sz);
1774 vcc->dev_data = NULL;
1776 return -EINVAL;
1778 ia_vcc->vc_desc_cnt = 0;
1779 ia_vcc->txing = 1;
1782 if (vcc->qos.txtp.max_pcr == ATM_MAX_PCR)
1783 vcc->qos.txtp.pcr = iadev->LineRate;
1784 else if ((vcc->qos.txtp.max_pcr == 0)&&( vcc->qos.txtp.pcr <= 0))
1785 vcc->qos.txtp.pcr = iadev->LineRate;
1786 else if ((vcc->qos.txtp.max_pcr > vcc->qos.txtp.pcr) && (vcc->qos.txtp.max_pcr> 0))
1787 vcc->qos.txtp.pcr = vcc->qos.txtp.max_pcr;
1788 if (vcc->qos.txtp.pcr > iadev->LineRate)
1789 vcc->qos.txtp.pcr = iadev->LineRate;
1790 ia_vcc->pcr = vcc->qos.txtp.pcr;
1792 if (ia_vcc->pcr > (iadev->LineRate / 6) ) ia_vcc->ltimeout = HZ / 10;
1793 else if (ia_vcc->pcr > (iadev->LineRate / 130)) ia_vcc->ltimeout = HZ;
1794 else if (ia_vcc->pcr <= 170) ia_vcc->ltimeout = 16 * HZ;
1795 else ia_vcc->ltimeout = 2700 * HZ / ia_vcc->pcr;
1796 if (ia_vcc->pcr < iadev->rate_limit)
1797 skb_queue_head_init (&ia_vcc->txing_skb);
1798 if (ia_vcc->pcr < iadev->rate_limit) {
1801 if (vcc->qos.txtp.max_sdu != 0) {
1802 if (ia_vcc->pcr > 60000)
1803 sk->sk_sndbuf = vcc->qos.txtp.max_sdu * 5;
1804 else if (ia_vcc->pcr > 2000)
1805 sk->sk_sndbuf = vcc->qos.txtp.max_sdu * 4;
1807 sk->sk_sndbuf = vcc->qos.txtp.max_sdu * 3;
1810 sk->sk_sndbuf = 24576;
1813 vc = (struct main_vc *)iadev->MAIN_VC_TABLE_ADDR;
1814 evc = (struct ext_vc *)iadev->EXT_VC_TABLE_ADDR;
1815 vc += vcc->vci;
1816 evc += vcc->vci;
1825 evc->atm_hdr1 = (vcc->vci >> 12) & 0x000f;
1826 evc->atm_hdr2 = (vcc->vci & 0x0fff) << 4;
1829 if (vcc->qos.txtp.traffic_class == ATM_UBR)
1831 vc->type = UBR;
1832 vc->status = CRC_APPEND;
1833 vc->acr = cellrate_to_float(iadev->LineRate);
1834 if (vcc->qos.txtp.pcr > 0)
1835 vc->acr = cellrate_to_float(vcc->qos.txtp.pcr);
1837 vcc->qos.txtp.max_pcr,vc->acr);)
1839 else if (vcc->qos.txtp.traffic_class == ATM_ABR)
1843 if (vcc->qos.txtp.pcr > 0)
1844 srv_p.pcr = vcc->qos.txtp.pcr;
1845 if (vcc->qos.txtp.min_pcr > 0) {
1846 int tmpsum = iadev->sum_mcr+iadev->sum_cbr+vcc->qos.txtp.min_pcr;
1847 if (tmpsum > iadev->LineRate)
1848 return -EBUSY;
1849 srv_p.mcr = vcc->qos.txtp.min_pcr;
1850 iadev->sum_mcr += vcc->qos.txtp.min_pcr;
1853 if (vcc->qos.txtp.icr)
1854 srv_p.icr = vcc->qos.txtp.icr;
1855 if (vcc->qos.txtp.tbe)
1856 srv_p.tbe = vcc->qos.txtp.tbe;
1857 if (vcc->qos.txtp.frtt)
1858 srv_p.frtt = vcc->qos.txtp.frtt;
1859 if (vcc->qos.txtp.rif)
1860 srv_p.rif = vcc->qos.txtp.rif;
1861 if (vcc->qos.txtp.rdf)
1862 srv_p.rdf = vcc->qos.txtp.rdf;
1863 if (vcc->qos.txtp.nrm_pres)
1864 srv_p.nrm = vcc->qos.txtp.nrm;
1865 if (vcc->qos.txtp.trm_pres)
1866 srv_p.trm = vcc->qos.txtp.trm;
1867 if (vcc->qos.txtp.adtf_pres)
1868 srv_p.adtf = vcc->qos.txtp.adtf;
1869 if (vcc->qos.txtp.cdf_pres)
1870 srv_p.cdf = vcc->qos.txtp.cdf;
1873 IF_ABR(printk("ABR:vcc->qos.txtp.max_pcr = %d mcr = %d\n",
1876 } else if (vcc->qos.txtp.traffic_class == ATM_CBR) {
1877 if (iadev->phy_type & FE_25MBIT_PHY) {
1879 return -EINVAL;
1881 if (vcc->qos.txtp.max_pcr > iadev->LineRate) {
1883 return -1;
1885 vc->type = CBR;
1886 vc->status = CRC_APPEND;
1894 iadev->testTable[vcc->vci]->vc_status |= VC_ACTIVE;
1917 spin_lock_init(&iadev->tx_lock);
1919 IF_INIT(printk("Tx MASK REG: 0x%0x\n",
1920 readw(iadev->seg_reg+SEG_MASK_REG));)
1923 dle_addr = dma_alloc_coherent(&iadev->pci->dev, DLE_TOTAL_SIZE,
1924 &iadev->tx_dle_dma, GFP_KERNEL);
1929 iadev->tx_dle_q.start = (struct dle*)dle_addr;
1930 iadev->tx_dle_q.read = iadev->tx_dle_q.start;
1931 iadev->tx_dle_q.write = iadev->tx_dle_q.start;
1932 iadev->tx_dle_q.end = (struct dle*)((unsigned long)dle_addr+sizeof(struct dle)*DLE_ENTRIES);
1935 writel(iadev->tx_dle_dma & 0xfffff000,
1936 iadev->dma + IPHASE5575_TX_LIST_ADDR);
1937 writew(0xffff, iadev->seg_reg+SEG_MASK_REG);
1938 writew(0, iadev->seg_reg+MODE_REG_0);
1939 writew(RESET_SEG, iadev->seg_reg+SEG_COMMAND_REG);
1940 iadev->MAIN_VC_TABLE_ADDR = iadev->seg_ram+MAIN_VC_TABLE*iadev->memSize;
1941 iadev->EXT_VC_TABLE_ADDR = iadev->seg_ram+EXT_VC_TABLE*iadev->memSize;
1942 iadev->ABR_SCHED_TABLE_ADDR=iadev->seg_ram+ABR_SCHED_TABLE*iadev->memSize;
1946 --------------------------------
1947 Buffer descr 0x0000 (128 - 4K)
1949 (512 - 1K) each
1950 TCQ - 4K, PRQ - 5K
1951 CBR Table 0x1800 (as needed) - 6K
1952 UBR Table 0x3000 (1K - 4K) - 12K
1953 UBR Wait queue 0x4000 (1K - 4K) - 16K
1954 ABR sched 0x5000 and ABR wait queue (1K - 2K) each
1955 ABR Tbl - 20K, ABR Wq - 22K
1956 extended VC 0x6000 (1K - 8K) - 24K
1957 VC Table 0x8000 (1K - 32K) - 32K
1964 writew(TX_DESC_BASE, iadev->seg_reg+SEG_DESC_BASE);
1967 buf_desc_ptr =(struct tx_buf_desc *)(iadev->seg_ram+TX_DESC_BASE);
1971 for(i=1; i<=iadev->num_tx_desc; i++)
1974 buf_desc_ptr->desc_mode = AAL5;
1975 buf_desc_ptr->buf_start_hi = tx_pkt_start >> 16;
1976 buf_desc_ptr->buf_start_lo = tx_pkt_start & 0x0000ffff;
1978 tx_pkt_start += iadev->tx_buf_sz;
1980 iadev->tx_buf = kmalloc_array(iadev->num_tx_desc,
1981 sizeof(*iadev->tx_buf),
1983 if (!iadev->tx_buf) {
1987 for (i= 0; i< iadev->num_tx_desc; i++)
1996 iadev->tx_buf[i].cpcs = cpcs;
1997 iadev->tx_buf[i].dma_addr = dma_map_single(&iadev->pci->dev,
2002 iadev->desc_tbl = kmalloc_array(iadev->num_tx_desc,
2003 sizeof(*iadev->desc_tbl),
2005 if (!iadev->desc_tbl) {
2011 i = TX_COMP_Q * iadev->memSize;
2012 writew(i >> 16, iadev->seg_reg+SEG_QUEUE_BASE);
2015 writew(i, iadev->seg_reg+TCQ_ST_ADR);
2016 writew(i, iadev->seg_reg+TCQ_RD_PTR);
2017 writew(i+iadev->num_tx_desc*sizeof(u_short),iadev->seg_reg+TCQ_WR_PTR);
2018 iadev->host_tcq_wr = i + iadev->num_tx_desc*sizeof(u_short);
2019 writew(i+2 * iadev->num_tx_desc * sizeof(u_short),
2020 iadev->seg_reg+TCQ_ED_ADR);
2022 tcq_st_adr = readw(iadev->seg_reg+TCQ_ST_ADR);
2023 tcq_start = (u_short *)(iadev->seg_ram+tcq_st_adr);
2024 for(i=1; i<=iadev->num_tx_desc; i++)
2031 i = PKT_RDY_Q * iadev->memSize;
2032 writew(i, iadev->seg_reg+PRQ_ST_ADR);
2033 writew(i+2 * iadev->num_tx_desc * sizeof(u_short),
2034 iadev->seg_reg+PRQ_ED_ADR);
2035 writew(i, iadev->seg_reg+PRQ_RD_PTR);
2036 writew(i, iadev->seg_reg+PRQ_WR_PTR);
2039 iadev->ffL.prq_st = readw(iadev->seg_reg+PRQ_ST_ADR) & 0xffff;
2040 iadev->ffL.prq_ed = readw(iadev->seg_reg+PRQ_ED_ADR) & 0xffff;
2041 iadev->ffL.prq_wr = readw(iadev->seg_reg+PRQ_WR_PTR) & 0xffff;
2043 iadev->ffL.tcq_st = readw(iadev->seg_reg+TCQ_ST_ADR) & 0xffff;
2044 iadev->ffL.tcq_ed = readw(iadev->seg_reg+TCQ_ED_ADR) & 0xffff;
2045 iadev->ffL.tcq_rd = readw(iadev->seg_reg+TCQ_RD_PTR) & 0xffff;
2049 prq_st_adr = readw(iadev->seg_reg+PRQ_ST_ADR);
2050 prq_start = (u_short *)(iadev->seg_ram+prq_st_adr);
2051 for(i=1; i<=iadev->num_tx_desc; i++)
2059 writew(0,iadev->seg_reg+CBR_PTR_BASE);
2061 tmp16 = (iadev->seg_ram+CBR_SCHED_TABLE*iadev->memSize)>>17;
2063 writew(tmp16,iadev->seg_reg+CBR_PTR_BASE);
2067 readw(iadev->seg_reg+CBR_PTR_BASE));)
2068 tmp16 = (CBR_SCHED_TABLE*iadev->memSize) >> 1;
2069 writew(tmp16, iadev->seg_reg+CBR_TAB_BEG);
2070 IF_INIT(printk("cbr_tab_beg = 0x%x in reg = 0x%x \n", tmp16,
2071 readw(iadev->seg_reg+CBR_TAB_BEG));)
2072 writew(tmp16, iadev->seg_reg+CBR_TAB_END+1); // CBR_PTR;
2073 tmp16 = (CBR_SCHED_TABLE*iadev->memSize + iadev->num_vc*6 - 2) >> 1;
2074 writew(tmp16, iadev->seg_reg+CBR_TAB_END);
2075 IF_INIT(printk("iadev->seg_reg = 0x%p CBR_PTR_BASE = 0x%x\n",
2076 iadev->seg_reg, readw(iadev->seg_reg+CBR_PTR_BASE));)
2078 readw(iadev->seg_reg+CBR_TAB_BEG), readw(iadev->seg_reg+CBR_TAB_END),
2079 readw(iadev->seg_reg+CBR_TAB_END+1));)
2082 memset_io(iadev->seg_ram+CBR_SCHED_TABLE*iadev->memSize,
2083 0, iadev->num_vc*6);
2084 iadev->CbrRemEntries = iadev->CbrTotEntries = iadev->num_vc*3;
2085 iadev->CbrEntryPt = 0;
2086 iadev->Granularity = MAX_ATM_155 / iadev->CbrTotEntries;
2087 iadev->NumEnabledCBR = 0;
2091 - SCHEDSZ is 1K (# of entries).
2092 - UBR Table size is 4K
2093 - UBR wait queue is 4K
2100 while (i != iadev->num_vc) {
2105 i = MAIN_VC_TABLE * iadev->memSize;
2106 writew(vcsize_sel | ((i >> 8) & 0xfff8),iadev->seg_reg+VCT_BASE);
2107 i = EXT_VC_TABLE * iadev->memSize;
2108 writew((i >> 8) & 0xfffe, iadev->seg_reg+VCTE_BASE);
2109 i = UBR_SCHED_TABLE * iadev->memSize;
2110 writew((i & 0xffff) >> 11, iadev->seg_reg+UBR_SBPTR_BASE);
2111 i = UBR_WAIT_Q * iadev->memSize;
2112 writew((i >> 7) & 0xffff, iadev->seg_reg+UBRWQ_BASE);
2113 memset((caddr_t)(iadev->seg_ram+UBR_SCHED_TABLE*iadev->memSize),
2114 0, iadev->num_vc*8);
2115 /* ABR scheduling Table(0x5000-0x57ff) and wait queue(0x5800-0x5fff)*/
2117 - SCHEDSZ is 1K (# of entries).
2118 - ABR Table size is 2K
2119 - ABR wait queue is 2K
2123 i = ABR_SCHED_TABLE * iadev->memSize;
2124 writew((i >> 11) & 0xffff, iadev->seg_reg+ABR_SBPTR_BASE);
2125 i = ABR_WAIT_Q * iadev->memSize;
2126 writew((i >> 7) & 0xffff, iadev->seg_reg+ABRWQ_BASE);
2128 i = ABR_SCHED_TABLE*iadev->memSize;
2129 memset((caddr_t)(iadev->seg_ram+i), 0, iadev->num_vc*4);
2130 vc = (struct main_vc *)iadev->MAIN_VC_TABLE_ADDR;
2131 evc = (struct ext_vc *)iadev->EXT_VC_TABLE_ADDR;
2132 iadev->testTable = kmalloc_array(iadev->num_vc,
2133 sizeof(*iadev->testTable),
2135 if (!iadev->testTable) {
2139 for(i=0; i<iadev->num_vc; i++)
2143 iadev->testTable[i] = kmalloc(sizeof(struct testTable_t),
2145 if (!iadev->testTable[i])
2147 iadev->testTable[i]->lastTime = 0;
2148 iadev->testTable[i]->fract = 0;
2149 iadev->testTable[i]->vc_status = VC_UBR;
2157 if (iadev->phy_type & FE_25MBIT_PHY) {
2158 writew(RATE25, iadev->seg_reg+MAXRATE);
2159 writew((UBR_EN | (0x23 << 2)), iadev->seg_reg+STPARMS);
2162 writew(cellrate_to_float(iadev->LineRate),iadev->seg_reg+MAXRATE);
2163 writew((UBR_EN | ABR_EN | (0x23 << 2)), iadev->seg_reg+STPARMS);
2166 writew(0, iadev->seg_reg+IDLEHEADHI);
2167 writew(0, iadev->seg_reg+IDLEHEADLO);
2170 writew(0xaa00, iadev->seg_reg+ABRUBR_ARB);
2172 iadev->close_pending = 0;
2173 init_waitqueue_head(&iadev->close_wait);
2174 init_waitqueue_head(&iadev->timeout_wait);
2175 skb_queue_head_init(&iadev->tx_dma_q);
2176 ia_init_rtn_q(&iadev->tx_return_q);
2179 writew(RM_TYPE_4_0, iadev->seg_reg+RM_TYPE);
2180 skb_queue_head_init (&iadev->tx_backlog);
2183 writew(MODE_REG_1_VAL, iadev->seg_reg+MODE_REG_1);
2186 writew(T_ONLINE, iadev->seg_reg+MODE_REG_0);
2188 /* Interrupt Status Register - read to clear */
2189 readw(iadev->seg_reg+SEG_INTR_STATUS_REG);
2191 /* Interrupt Mask Reg- don't mask TCQ_NOT_EMPTY interrupt generation */
2192 writew(~(TRANSMIT_DONE | TCQ_NOT_EMPTY), iadev->seg_reg+SEG_MASK_REG);
2193 writew(TRANSMIT_DONE, iadev->seg_reg+SEG_INTR_STATUS_REG);
2194 iadev->tx_pkt_cnt = 0;
2195 iadev->rate_limit = iadev->LineRate / 3;
2200 while (--i >= 0)
2201 kfree(iadev->testTable[i]);
2202 kfree(iadev->testTable);
2204 kfree(iadev->desc_tbl);
2206 i = iadev->num_tx_desc;
2208 while (--i >= 0) {
2209 struct cpcs_trailer_desc *desc = iadev->tx_buf + i;
2211 dma_unmap_single(&iadev->pci->dev, desc->dma_addr,
2212 sizeof(*desc->cpcs), DMA_TO_DEVICE);
2213 kfree(desc->cpcs);
2215 kfree(iadev->tx_buf);
2217 dma_free_coherent(&iadev->pci->dev, DLE_TOTAL_SIZE, iadev->tx_dle_q.start,
2218 iadev->tx_dle_dma);
2220 return -ENOMEM;
2232 while( (status = readl(iadev->reg+IPHASE5575_BUS_STATUS_REG) & 0x7f))
2239 IF_EVENT(printk("REASSINT Bus status reg: %08x\n", status);)
2245 writel(STAT_DLERINT, iadev->reg + IPHASE5575_BUS_STATUS_REG);
2256 writel(STAT_DLETINT, iadev->reg + IPHASE5575_BUS_STATUS_REG);
2270 /*----------------------------- entries --------------------------------*/
2280 iadev->reg+IPHASE5575_MAC1)));
2281 mac2 = cpu_to_be16(le16_to_cpu(readl(iadev->reg+IPHASE5575_MAC2)));
2284 dev->esi[i] = mac1 >>(8*(MAC1_LEN-1-i));
2287 dev->esi[i+MAC1_LEN] = mac2 >>(8*(MAC2_LEN - 1 -i));
2299 if ((error = pci_read_config_dword(iadev->pci,
2302 writel(0, iadev->reg+IPHASE5575_EXT_RESET);
2304 if ((error = pci_write_config_dword(iadev->pci,
2325 dev->ci_range.vpi_bits = 0;
2326 dev->ci_range.vci_bits = NR_VCI_LD;
2329 real_base = pci_resource_start (iadev->pci, 0);
2330 iadev->irq = iadev->pci->irq;
2332 error = pci_read_config_word(iadev->pci, PCI_COMMAND, &command);
2335 dev->number,error);
2336 return -EINVAL;
2339 dev->number, iadev->pci->revision, real_base, iadev->irq);)
2343 iadev->pci_map_size = pci_resource_len(iadev->pci, 0);
2345 if (iadev->pci_map_size == 0x100000){
2346 iadev->num_vc = 4096;
2347 dev->ci_range.vci_bits = NR_VCI_4K_LD;
2348 iadev->memSize = 4;
2350 else if (iadev->pci_map_size == 0x40000) {
2351 iadev->num_vc = 1024;
2352 iadev->memSize = 1;
2355 printk("Unknown pci_map_size = 0x%x\n", iadev->pci_map_size);
2356 return -EINVAL;
2358 IF_INIT(printk (DEV_LABEL "map size: %i\n", iadev->pci_map_size);)
2361 pci_set_master(iadev->pci);
2369 base = ioremap(real_base,iadev->pci_map_size); /* ioremap is not resolved ??? */
2374 dev->number);
2375 return -ENOMEM;
2378 dev->number, iadev->pci->revision, base, iadev->irq);)
2381 iadev->mem = iadev->pci_map_size /2;
2382 iadev->real_base = real_base;
2383 iadev->base = base;
2386 iadev->reg = base + REG_BASE;
2388 iadev->seg_reg = base + SEG_BASE;
2390 iadev->reass_reg = base + REASS_BASE;
2392 iadev->phy = base + PHY_BASE;
2393 iadev->dma = base + PHY_BASE;
2394 /* RAM - Segmentation RAm and Reassembly RAM */
2395 iadev->ram = base + ACTUAL_RAM_BASE;
2396 iadev->seg_ram = base + ACTUAL_SEG_RAM_BASE;
2397 iadev->reass_ram = base + ACTUAL_REASS_RAM_BASE;
2401 iadev->reg,iadev->seg_reg,iadev->reass_reg,
2402 iadev->phy, iadev->ram, iadev->seg_ram,
2403 iadev->reass_ram);)
2408 iounmap(iadev->base);
2413 printk("%s%02X",i ? "-" : "",dev->esi[i]);
2418 iounmap(iadev->base);
2426 if (!iadev->carrier_detect)
2428 iadev->rx_cell_cnt += readw(iadev->reass_reg+CELL_CTR0)&0xffff;
2429 iadev->rx_cell_cnt += (readw(iadev->reass_reg+CELL_CTR1) & 0xffff) << 16;
2430 iadev->drop_rxpkt += readw(iadev->reass_reg + DRP_PKT_CNTR ) & 0xffff;
2431 iadev->drop_rxcell += readw(iadev->reass_reg + ERR_CNTR) & 0xffff;
2432 iadev->tx_cell_cnt += readw(iadev->seg_reg + CELL_CTR_LO_AUTO)&0xffff;
2433 iadev->tx_cell_cnt += (readw(iadev->seg_reg+CELL_CTR_HIGH_AUTO)&0xffff)<<16;
2444 ctrl_reg = readl(ia_dev[i]->reg+IPHASE5575_BUS_CONTROL_REG);
2448 writel(ctrl_reg, ia_dev[i]->reg+IPHASE5575_BUS_CONTROL_REG);
2454 writel(ctrl_reg, ia_dev[i]->reg+IPHASE5575_BUS_CONTROL_REG);
2455 spin_lock_irqsave(&ia_dev[i]->tx_lock, flags);
2456 if (ia_dev[i]->close_pending)
2457 wake_up(&ia_dev[i]->close_wait);
2459 spin_unlock_irqrestore(&ia_dev[i]->tx_lock, flags);
2470 writel(value, INPH_IA_DEV(dev)->phy+addr);
2475 return readl(INPH_IA_DEV(dev)->phy+addr);
2482 kfree(iadev->desc_tbl);
2483 for (i = 0; i < iadev->num_vc; i++)
2484 kfree(iadev->testTable[i]);
2485 kfree(iadev->testTable);
2486 for (i = 0; i < iadev->num_tx_desc; i++) {
2487 struct cpcs_trailer_desc *desc = iadev->tx_buf + i;
2489 dma_unmap_single(&iadev->pci->dev, desc->dma_addr,
2490 sizeof(*desc->cpcs), DMA_TO_DEVICE);
2491 kfree(desc->cpcs);
2493 kfree(iadev->tx_buf);
2494 dma_free_coherent(&iadev->pci->dev, DLE_TOTAL_SIZE, iadev->tx_dle_q.start,
2495 iadev->tx_dle_dma);
2500 kfree(iadev->rx_open);
2501 dma_free_coherent(&iadev->pci->dev, DLE_TOTAL_SIZE, iadev->rx_dle_q.start,
2502 iadev->rx_dle_dma);
2513 if (request_irq(iadev->irq, &ia_int, IRQF_SHARED, DEV_LABEL, dev)) {
2515 dev->number, iadev->irq);
2516 error = -EAGAIN;
2521 if ((error = pci_write_config_word(iadev->pci,
2526 "master (0x%x)\n",dev->number, error);
2527 error = -EIO;
2535 IF_INIT(printk("Bus ctrl reg: %08x\n",
2536 readl(iadev->reg+IPHASE5575_BUS_CONTROL_REG));)
2537 ctrl_reg = readl(iadev->reg+IPHASE5575_BUS_CONTROL_REG);
2553 writel(ctrl_reg, iadev->reg+IPHASE5575_BUS_CONTROL_REG);
2555 IF_INIT(printk("Bus ctrl reg after initializing: %08x\n",
2556 readl(iadev->reg+IPHASE5575_BUS_CONTROL_REG));
2557 printk("Bus status reg after init: %08x\n",
2558 readl(iadev->reg+IPHASE5575_BUS_STATUS_REG));)
2568 ctrl_reg = readl(iadev->reg+IPHASE5575_BUS_CONTROL_REG);
2569 writel(ctrl_reg | CTRL_FE_RST, iadev->reg+IPHASE5575_BUS_CONTROL_REG);
2570 IF_INIT(printk("Bus ctrl reg after initializing: %08x\n",
2571 readl(iadev->reg+IPHASE5575_BUS_CONTROL_REG));)
2579 if (iadev->phy_type & FE_25MBIT_PHY)
2581 else if (iadev->phy_type & (FE_DS3_PHY | FE_E3_PHY))
2587 if (dev->phy->start) {
2588 error = dev->phy->start(dev);
2592 /* Get iadev->carrier_detect status */
2602 free_irq(iadev->irq, dev);
2617 iadev = INPH_IA_DEV(vcc->dev);
2621 IF_EVENT(printk("ia_close: ia_vcc->vc_desc_cnt = %d vci = %d\n",
2622 ia_vcc->vc_desc_cnt,vcc->vci);)
2623 clear_bit(ATM_VF_READY,&vcc->flags);
2626 if (vcc->qos.txtp.traffic_class != ATM_NONE) {
2627 iadev->close_pending++;
2628 prepare_to_wait(&iadev->timeout_wait, &wait, TASK_UNINTERRUPTIBLE);
2630 finish_wait(&iadev->timeout_wait, &wait);
2631 spin_lock_irqsave(&iadev->tx_lock, flags);
2632 while((skb = skb_dequeue(&iadev->tx_backlog))) {
2633 if (ATM_SKB(skb)->vcc == vcc){
2634 if (vcc->pop) vcc->pop(vcc, skb);
2641 skb_queue_tail(&iadev->tx_backlog, skb);
2642 IF_EVENT(printk("IA TX Done decs_cnt = %d\n", ia_vcc->vc_desc_cnt);)
2643 closetime = 300000 / ia_vcc->pcr;
2646 spin_unlock_irqrestore(&iadev->tx_lock, flags);
2647 wait_event_timeout(iadev->close_wait, (ia_vcc->vc_desc_cnt <= 0), closetime);
2648 spin_lock_irqsave(&iadev->tx_lock, flags);
2649 iadev->close_pending--;
2650 iadev->testTable[vcc->vci]->lastTime = 0;
2651 iadev->testTable[vcc->vci]->fract = 0;
2652 iadev->testTable[vcc->vci]->vc_status = VC_UBR;
2653 if (vcc->qos.txtp.traffic_class == ATM_ABR) {
2654 if (vcc->qos.txtp.min_pcr > 0)
2655 iadev->sum_mcr -= vcc->qos.txtp.min_pcr;
2657 if (vcc->qos.txtp.traffic_class == ATM_CBR) {
2659 iadev->sum_mcr -= ia_vcc->NumCbrEntry*iadev->Granularity;
2662 spin_unlock_irqrestore(&iadev->tx_lock, flags);
2665 if (vcc->qos.rxtp.traffic_class != ATM_NONE) {
2667 vc_table = (u16 *)(iadev->reass_ram+REASS_TABLE*iadev->memSize);
2668 vc_table += vcc->vci;
2671 vc_table = (u16 *)(iadev->reass_ram+RX_VC_TABLE*iadev->memSize);
2672 vc_table += vcc->vci;
2673 *vc_table = (vcc->vci << 6) | 15;
2674 if (vcc->qos.rxtp.traffic_class == ATM_ABR) {
2676 (iadev->reass_ram+ABR_VC_TABLE*iadev->memSize);
2677 abr_vc_table += vcc->vci;
2678 abr_vc_table->rdf = 0x0003;
2679 abr_vc_table->air = 0x5eb1;
2682 rx_dle_intr(vcc->dev);
2683 iadev->rx_open[vcc->vci] = NULL;
2687 vcc->dev_data = NULL;
2688 clear_bit(ATM_VF_ADDR,&vcc->flags);
2696 if (!test_bit(ATM_VF_PARTIAL,&vcc->flags))
2699 vcc->dev_data = NULL;
2701 if (vcc->vci != ATM_VPI_UNSPEC && vcc->vpi != ATM_VCI_UNSPEC)
2704 set_bit(ATM_VF_ADDR,&vcc->flags);
2706 if (vcc->qos.aal != ATM_AAL5)
2707 return -EINVAL;
2709 vcc->dev->number, vcc->vpi, vcc->vci);)
2713 if (!ia_vcc) return -ENOMEM;
2714 vcc->dev_data = ia_vcc;
2730 set_bit(ATM_VF_READY,&vcc->flags);
2760 if (!dev->phy->ioctl) return -EINVAL;
2761 return dev->phy->ioctl(dev,cmd,arg);
2763 if (copy_from_user(&ia_cmds, arg, sizeof ia_cmds)) return -EFAULT;
2776 if (!capable(CAP_NET_ADMIN)) return -EPERM;
2779 if(put_user((u16)(readl(iadev->seg_reg+i) & 0xffff), tmps)) return -EFAULT;
2784 if (!capable(CAP_NET_ADMIN)) return -EPERM;
2787 if(put_user((u16)(readl(iadev->reass_reg+i) & 0xffff), tmps)) return -EFAULT;
2797 if (!capable(CAP_NET_ADMIN)) return -EPERM;
2799 if (!regs_local) return -ENOMEM;
2800 ffL = ®s_local->ffredn;
2801 rfL = ®s_local->rfredn;
2804 ((u_int *)rfL)[i] = readl(iadev->reass_reg + i) & 0xffff;
2807 ((u_int *)ffL)[i] = readl(iadev->seg_reg + i) & 0xffff;
2811 return -EFAULT;
2820 if (!capable(CAP_NET_ADMIN)) return -EPERM;
2828 printk("skb = 0x%p\n", skb_peek(&iadev->tx_backlog));
2829 printk("rtn_q: 0x%p\n",ia_deque_rtn_q(&iadev->tx_return_q));
2835 stats = &PRIV(_ia_dev[board])->sonet_stats;
2836 printk("section_bip: %d\n", atomic_read(&stats->section_bip));
2837 printk("line_bip : %d\n", atomic_read(&stats->line_bip));
2838 printk("path_bip : %d\n", atomic_read(&stats->path_bip));
2839 printk("line_febe : %d\n", atomic_read(&stats->line_febe));
2840 printk("path_febe : %d\n", atomic_read(&stats->path_febe));
2841 printk("corr_hcs : %d\n", atomic_read(&stats->corr_hcs));
2842 printk("uncorr_hcs : %d\n", atomic_read(&stats->uncorr_hcs));
2843 printk("tx_cells : %d\n", atomic_read(&stats->tx_cells));
2844 printk("rx_cells : %d\n", atomic_read(&stats->rx_cells));
2849 if (!capable(CAP_NET_ADMIN)) return -EPERM;
2850 for (i = 1; i <= iadev->num_rx_desc; i++)
2853 iadev->reass_reg+REASS_MASK_REG);
2854 iadev->rxing = 1;
2860 if (!capable(CAP_NET_ADMIN)) return -EPERM;
2864 if (!capable(CAP_NET_ADMIN)) return -EPERM;
2894 iadev = INPH_IA_DEV(vcc->dev);
2896 if (!iavcc->txing) {
2898 if (vcc->pop)
2899 vcc->pop(vcc, skb);
2905 if (skb->len > iadev->tx_buf_sz - 8) {
2907 if (vcc->pop)
2908 vcc->pop(vcc, skb);
2913 if ((unsigned long)skb->data & 3) {
2915 if (vcc->pop)
2916 vcc->pop(vcc, skb);
2932 if ((desc == 0) || (desc > iadev->num_tx_desc))
2935 atomic_inc(&vcc->stats->tx);
2936 if (vcc->pop)
2937 vcc->pop(vcc, skb);
2950 iavcc->vc_desc_cnt++;
2951 iadev->desc_tbl[desc-1].iavcc = iavcc;
2952 iadev->desc_tbl[desc-1].txskb = skb;
2955 iadev->ffL.tcq_rd += 2;
2956 if (iadev->ffL.tcq_rd > iadev->ffL.tcq_ed)
2957 iadev->ffL.tcq_rd = iadev->ffL.tcq_st;
2958 writew(iadev->ffL.tcq_rd, iadev->seg_reg+TCQ_RD_PTR);
2963 *(u16*)(iadev->seg_ram+iadev->ffL.prq_wr) = desc;
2965 iadev->ffL.prq_wr += 2;
2966 if (iadev->ffL.prq_wr > iadev->ffL.prq_ed)
2967 iadev->ffL.prq_wr = iadev->ffL.prq_st;
2971 total_len = skb->len + sizeof(struct cpcs_trailer);
2973 IF_TX(printk("ia packet len:%d padding:%d\n", total_len, total_len - skb->len);)
2976 trailer = iadev->tx_buf[desc-1].cpcs;
2977 IF_TX(printk("Sent: skb = 0x%p skb->data: 0x%p len: %d, desc: %d\n",
2978 skb, skb->data, skb->len, desc);)
2979 trailer->control = 0;
2981 trailer->length = ((skb->len & 0xff) << 8) | ((skb->len & 0xff00) >> 8);
2982 trailer->crc32 = 0; /* not needed - dummy bytes */
2986 skb->len, tcnter++);
2987 xdump(skb->data, skb->len, "TX: ");
2991 buf_desc_ptr = iadev->seg_ram+TX_DESC_BASE;
2993 buf_desc_ptr->desc_mode = AAL5 | EOM_EN | APP_CRC32 | CMPL_INT;
2994 /* Huh ? p.115 of users guide describes this as a read-only register */
2995 writew(TRANSMIT_DONE, iadev->seg_reg+SEG_INTR_STATUS_REG);
2996 buf_desc_ptr->vc_index = vcc->vci;
2997 buf_desc_ptr->bytes = total_len;
2999 if (vcc->qos.txtp.traffic_class == ATM_ABR)
3003 wr_ptr = iadev->tx_dle_q.write;
3005 wr_ptr->sys_pkt_addr = dma_map_single(&iadev->pci->dev, skb->data,
3006 skb->len, DMA_TO_DEVICE);
3007 wr_ptr->local_pkt_addr = (buf_desc_ptr->buf_start_hi << 16) |
3008 buf_desc_ptr->buf_start_lo;
3009 /* wr_ptr->bytes = swap_byte_order(total_len); didn't seem to affect?? */
3010 wr_ptr->bytes = skb->len;
3012 /* hw bug - DLEs of 0x2d, 0x2e, 0x2f cause DMA lockup */
3013 if ((wr_ptr->bytes >> 2) == 0xb)
3014 wr_ptr->bytes = 0x30;
3016 wr_ptr->mode = TX_DLE_PSI;
3017 wr_ptr->prq_wr_ptr_data = 0;
3020 if (++wr_ptr == iadev->tx_dle_q.end)
3021 wr_ptr = iadev->tx_dle_q.start;
3024 wr_ptr->sys_pkt_addr = iadev->tx_buf[desc-1].dma_addr;
3025 wr_ptr->local_pkt_addr = ((buf_desc_ptr->buf_start_hi << 16) |
3026 buf_desc_ptr->buf_start_lo) + total_len - sizeof(struct cpcs_trailer);
3028 wr_ptr->bytes = sizeof(struct cpcs_trailer);
3029 wr_ptr->mode = DMA_INT_ENABLE;
3030 wr_ptr->prq_wr_ptr_data = iadev->ffL.prq_wr;
3033 if (++wr_ptr == iadev->tx_dle_q.end)
3034 wr_ptr = iadev->tx_dle_q.start;
3036 iadev->tx_dle_q.write = wr_ptr;
3037 ATM_DESC(skb) = vcc->vci;
3038 skb_queue_tail(&iadev->tx_dma_q, skb);
3040 atomic_inc(&vcc->stats->tx);
3041 iadev->tx_pkt_cnt++;
3043 writel(2, iadev->dma+IPHASE5575_TX_COUNTER);
3047 if (atomic_read(&vcc->stats->tx) % 20 == 0) {
3048 if (iavcc->vc_desc_cnt > 10) {
3049 vcc->tx_quota = vcc->tx_quota * 3 / 4;
3050 printk("Tx1: vcc->tx_quota = %d \n", (u32)vcc->tx_quota );
3051 iavcc->flow_inc = -1;
3052 iavcc->saved_tx_quota = vcc->tx_quota;
3053 } else if ((iavcc->flow_inc < 0) && (iavcc->vc_desc_cnt < 3)) {
3054 // vcc->tx_quota = 3 * iavcc->saved_tx_quota / 4;
3055 printk("Tx2: vcc->tx_quota = %d \n", (u32)vcc->tx_quota );
3056 iavcc->flow_inc = 0;
3069 iadev = INPH_IA_DEV(vcc->dev);
3070 if ((!skb)||(skb->len>(iadev->tx_buf_sz-sizeof(struct cpcs_trailer))))
3075 return -EINVAL;
3077 spin_lock_irqsave(&iadev->tx_lock, flags);
3078 if (!test_bit(ATM_VF_READY,&vcc->flags)){
3080 spin_unlock_irqrestore(&iadev->tx_lock, flags);
3081 return -EINVAL;
3083 ATM_SKB(skb)->vcc = vcc;
3085 if (skb_peek(&iadev->tx_backlog)) {
3086 skb_queue_tail(&iadev->tx_backlog, skb);
3090 skb_queue_tail(&iadev->tx_backlog, skb);
3093 spin_unlock_irqrestore(&iadev->tx_lock, flags);
3103 if(!left--) {
3104 if (iadev->phy_type == FE_25MBIT_PHY) {
3105 n = sprintf(page, " Board Type : Iphase5525-1KVC-128K\n");
3108 if (iadev->phy_type == FE_DS3_PHY)
3109 n = sprintf(page, " Board Type : Iphase-ATM-DS3");
3110 else if (iadev->phy_type == FE_E3_PHY)
3111 n = sprintf(page, " Board Type : Iphase-ATM-E3");
3112 else if (iadev->phy_type == FE_UTP_OPTION)
3113 n = sprintf(page, " Board Type : Iphase-ATM-UTP155");
3115 n = sprintf(page, " Board Type : Iphase-ATM-OC3");
3117 if (iadev->pci_map_size == 0x40000)
3118 n += sprintf(tmpPtr, "-1KVC-");
3120 n += sprintf(tmpPtr, "-4KVC-");
3122 if ((iadev->memType & MEM_SIZE_MASK) == MEM_SIZE_1M)
3124 else if ((iadev->memType & MEM_SIZE_MASK) == MEM_SIZE_512K)
3141 iadev->num_tx_desc, iadev->tx_buf_sz,
3142 iadev->num_rx_desc, iadev->rx_buf_sz,
3143 iadev->rx_pkt_cnt, iadev->tx_pkt_cnt,
3144 iadev->rx_cell_cnt, iadev->tx_cell_cnt,
3145 iadev->drop_rxcell, iadev->drop_rxpkt);
3170 ret = -ENOMEM;
3174 iadev->pci = pdev;
3177 pdev->bus->number, PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn));)
3179 ret = -ENODEV;
3182 dev = atm_dev_register(DEV_LABEL, &pdev->dev, &ops, -1, NULL);
3184 ret = -ENOMEM;
3187 dev->dev_data = iadev;
3188 IF_INIT(printk(DEV_LABEL "registered at (itf :%d)\n", dev->number);)
3189 IF_INIT(printk("dev_id = 0x%p iadev->LineRate = %d \n", dev,
3190 iadev->LineRate);)
3199 iadev_count--;
3202 ret = -EINVAL;
3207 iadev->next_board = ia_boards;
3232 if (dev->phy && dev->phy->stop)
3233 dev->phy->stop(dev);
3235 /* De-register device */
3236 free_irq(iadev->irq, dev);
3237 iadev_count--;
3240 IF_EVENT(printk("deregistering iav at (itf:%d)\n", dev->number);)
3243 iounmap(iadev->base);