Lines Matching +full:0 +full:xaa00
70 #define swap_byte_order(x) (((x & 0xff) << 8) | ((x & 0xff00) >> 8))
85 |IF_IADBG_ABR | IF_IADBG_EVENT*/ 0;
87 module_param(IA_TX_BUF, int, 0);
88 module_param(IA_TX_BUF_SZ, int, 0);
89 module_param(IA_RX_BUF, int, 0);
90 module_param(IA_RX_BUF_SZ, int, 0);
148 tcq_wr = readl(dev->seg_reg+TCQ_WR_PTR) & 0xffff; in ia_hack_tcq()
154 *(u_short *) (dev->seg_ram + dev->host_tcq_wr) = 0; in ia_hack_tcq()
162 dev->desc_tbl[desc1 -1].timestamp = 0; in ia_hack_tcq()
163 IF_EVENT(printk("ia_hack: return_q skb = 0x%p desc = %d\n", in ia_hack_tcq()
167 if (ia_enque_rtn_q(&dev->tx_return_q, dev->desc_tbl[desc1 -1]) < 0) in ia_hack_tcq()
183 static unsigned long timer = 0; in get_desc()
189 i=0; in get_desc()
208 dev->desc_tbl[i].timestamp = 0; in get_desc()
216 return 0xFFFF; in get_desc()
226 return 0xFFFF; in get_desc()
247 foundLockUp = 0; in clear_lockup()
248 if( vcstatus->cnt == 0x05 ) { in clear_lockup()
252 if( (abr_vc->status & 0x07) == ABR_STATE /* 0x2 */ ) { in clear_lockup()
255 if ((eabr_vc->last_desc)&&((abr_vc->status & 0x07)==ABR_STATE)) in clear_lockup()
268 vcstatus->cnt = 0; in clear_lockup()
273 writew(0xFFFD, dev->seg_reg+MODE_REG_0); in clear_lockup()
276 abr_vc->status &= 0xFFF8; in clear_lockup()
277 abr_vc->status |= 0x0001; /* state is idle */ in clear_lockup()
279 for( i = 0; ((i < dev->num_vc) && (shd_tbl[i])); i++ ); in clear_lockup()
287 vcstatus->cnt = 0; in clear_lockup()
302 ** R = reserved (written as 0)
303 ** NZ = 0 if 0 cells/sec; 1 otherwise
311 #define NZ 0x4000 in cellrate_to_float()
314 #define M_MASK 0x1ff in cellrate_to_float()
315 #define E_MASK 0x1f in cellrate_to_float()
317 u32 tmp = cr & 0x00ffffff; in cellrate_to_float()
318 int i = 0; in cellrate_to_float()
319 if (cr == 0) in cellrate_to_float()
320 return 0; in cellrate_to_float()
334 #if 0
342 if ((rate & NZ) == 0)
343 return 0;
346 if (exp == 0)
362 srv_p->mcr = 0; in init_abr_vc()
363 srv_p->icr = 0x055cb7; in init_abr_vc()
364 srv_p->tbe = 0xffffff; in init_abr_vc()
365 srv_p->frtt = 0x3a; in init_abr_vc()
366 srv_p->rif = 0xf; in init_abr_vc()
367 srv_p->rdf = 0xb; in init_abr_vc()
368 srv_p->nrm = 0x4; in init_abr_vc()
369 srv_p->trm = 0x7; in init_abr_vc()
370 srv_p->cdf = 0x3; in init_abr_vc()
387 #if 0 /* sanity check */ in ia_open_abr_vc()
388 if (srv_p->pcr == 0) in ia_open_abr_vc()
410 else if (srv_p->adtf == 0) in ia_open_abr_vc()
419 memset ((caddr_t)f_abr_vc, 0, sizeof(*f_abr_vc)); in ia_open_abr_vc()
425 if ( trm == 0) trm = 1; in ia_open_abr_vc()
426 f_abr_vc->f_nrmexp =(((srv_p->nrm +1) & 0x0f) << 12)|(MRM << 8) | trm; in ia_open_abr_vc()
428 if (crm == 0) crm = 1; in ia_open_abr_vc()
429 f_abr_vc->f_crm = crm & 0xff; in ia_open_abr_vc()
436 if (adtf == 0) adtf = 1; in ia_open_abr_vc()
437 f_abr_vc->f_cdf = ((7 - srv_p->cdf) << 12 | adtf) & 0xfff; in ia_open_abr_vc()
440 f_abr_vc->f_status = 0x0042; in ia_open_abr_vc()
442 case 0: /* RFRED initialization */ in ia_open_abr_vc()
447 r_abr_vc->r_status_rdf = (15 - srv_p->rdf) & 0x000f; in ia_open_abr_vc()
449 if (air == 0) air = 1; in ia_open_abr_vc()
458 return 0; in ia_open_abr_vc()
461 u32 rateLow=0, rateHigh, rate; in ia_cbr_setup()
465 int idealSlot =0, testSlot, toBeAssigned, inc; in ia_cbr_setup()
469 u32 fracSlot = 0; in ia_cbr_setup()
470 u32 sp_mod = 0; in ia_cbr_setup()
471 u32 sp_mod2 = 0; in ia_cbr_setup()
474 if (vcc->qos.txtp.max_pcr <= 0) { in ia_cbr_setup()
480 IF_CBR(printk("CBR: CBR entries=0x%x for rate=0x%x & Gran=0x%x\n", in ia_cbr_setup()
490 IF_CBR(printk("Entries = 0x%x, CbrRemEntries = 0x%x.\n", in ia_cbr_setup()
501 cbrVC = 0; in ia_cbr_setup()
505 fracSlot = 0; in ia_cbr_setup()
507 IF_CBR(printk("Vci=0x%x,Spacing=0x%x,Sp_mod=0x%x\n",vcIndex,spacing,sp_mod);) in ia_cbr_setup()
529 inc = 0; in ia_cbr_setup()
532 IF_CBR(printk("CBR Testslot 0x%x AT Location 0x%p, NumToAssign=%d\n", in ia_cbr_setup()
539 if (testSlot < 0) { // Wrap if necessary in ia_cbr_setup()
541 IF_CBR(printk("Testslot Wrap. STable Start=0x%p,Testslot=%d\n", in ia_cbr_setup()
552 IF_CBR(printk(" Testslot=0x%x ToBeAssgned=%d\n", in ia_cbr_setup()
557 IF_CBR(printk("Reading CBR Tbl from 0x%p, CbrVal=0x%x Iteration %d\n", in ia_cbr_setup()
570 writew((CBR_EN | UBR_EN | ABR_EN | (0x23 << 2)), dev->seg_reg+STPARMS); in ia_cbr_setup()
573 return 0; in ia_cbr_setup()
577 u16 *SchedTbl, NullVci = 0; in ia_cbrVc_close()
583 if (iadev->NumEnabledCBR == 0) { in ia_cbrVc_close()
584 writew((UBR_EN | ABR_EN | (0x23 << 2)), iadev->seg_reg+STPARMS); in ia_cbrVc_close()
587 NumFound = 0; in ia_cbrVc_close()
588 for (i=0; i < iadev->CbrTotEntries; i++) in ia_cbrVc_close()
601 int tmp = 0; in ia_avail_descs()
635 return 0; in ia_que_tx()
671 if ((vcc->pop) && (skb1->len != 0)) in ia_tx_poll()
674 IF_EVENT(printk("Transmit Done - skb 0x%lx return\n", in ia_tx_poll()
686 if ((vcc->pop) && (skb->len != 0)) in ia_tx_poll()
689 IF_EVENT(printk("Tx Done - skb 0x%lx return\n",(long)skb);) in ia_tx_poll()
699 #if 0
716 for (i=15; i>=0; i--) {
717 NVRAM_CLKOUT (val & 0x8000);
750 val = 0; in ia_eeprom_get()
751 for (i=15; i>=0; i--) { in ia_eeprom_get()
797 #if 0
807 IF_INIT(printk("memType = 0x%x iadev->phy_type = 0x%x\n",
837 iadev->carrier_detect = (status & MB25_IS_GSB) ? 1 : 0;
841 iadev->carrier_detect = (status & SUNI_DS3_LOSV) ? 0 : 1;
845 iadev->carrier_detect = (status & SUNI_E3_LOS) ? 0 : 1;
848 iadev->carrier_detect = (status & SUNI_LOSV) ? 0 : 1;
857 #if 0
861 ia_phy_write32(iadev, MB25_DIAG_CONTROL, 0);
864 (ia_phy_read32(iadev, MB25_INTR_STATUS) & MB25_IS_GSB) ? 1 : 0;
884 { SUNI_DS3_FRM_INTR_ENBL, 0x17 },
885 { SUNI_DS3_FRM_CFG, 0x01 },
886 { SUNI_DS3_TRAN_CFG, 0x01 },
887 { SUNI_CONFIG, 0 },
888 { SUNI_SPLR_CFG, 0 },
889 { SUNI_SPLT_CFG, 0 }
894 iadev->carrier_detect = (status & SUNI_DS3_LOSV) ? 0 : 1;
902 { SUNI_E3_FRM_FRAM_OPTIONS, 0x04 },
903 { SUNI_E3_FRM_MAINT_OPTIONS, 0x20 },
904 { SUNI_E3_FRM_FRAM_INTR_ENBL, 0x1d },
905 { SUNI_E3_FRM_MAINT_INTR_ENBL, 0x30 },
906 { SUNI_E3_TRAN_STAT_DIAG_OPTIONS, 0 },
907 { SUNI_E3_TRAN_FRAM_OPTIONS, 0x01 },
909 { SUNI_SPLR_CFG, 0x41 },
910 { SUNI_SPLT_CFG, 0x41 }
915 iadev->carrier_detect = (status & SUNI_E3_LOS) ? 0 : 1;
923 { SUNI_INTR_ENBL, 0x28 },
925 { SUNI_ID_RESET, 0 },
927 { SUNI_MASTER_TEST, 0 },
929 { SUNI_RXCP_CTRL, 0x2c },
930 { SUNI_RXCP_FCTRL, 0x81 },
932 { SUNI_RXCP_IDLE_PAT_H1, 0 },
933 { SUNI_RXCP_IDLE_PAT_H2, 0 },
934 { SUNI_RXCP_IDLE_PAT_H3, 0 },
935 { SUNI_RXCP_IDLE_PAT_H4, 0x01 },
937 { SUNI_RXCP_IDLE_MASK_H1, 0xff },
938 { SUNI_RXCP_IDLE_MASK_H2, 0xff },
939 { SUNI_RXCP_IDLE_MASK_H3, 0xff },
940 { SUNI_RXCP_IDLE_MASK_H4, 0xfe },
942 { SUNI_RXCP_CELL_PAT_H1, 0 },
943 { SUNI_RXCP_CELL_PAT_H2, 0 },
944 { SUNI_RXCP_CELL_PAT_H3, 0 },
945 { SUNI_RXCP_CELL_PAT_H4, 0x01 },
947 { SUNI_RXCP_CELL_MASK_H1, 0xff },
948 { SUNI_RXCP_CELL_MASK_H2, 0xff },
949 { SUNI_RXCP_CELL_MASK_H3, 0xff },
950 { SUNI_RXCP_CELL_MASK_H4, 0xff },
952 { SUNI_TXCP_CTRL, 0xa4 },
953 { SUNI_TXCP_INTR_EN_STS, 0x10 },
954 { SUNI_TXCP_IDLE_PAT_H5, 0x55 }
977 static int tcnter = 0;
983 count = 0;
986 for(col = 0;count + col < length && col < 16; col++){
987 if (col != 0 && (col % 4) == 0)
992 if ((col % 4) == 0)
997 for(col = 0;count + col < length && col < 16; col++){
1033 printk("B_tcq_wr = 0x%x desc = %d last desc = %d\n",
1036 printk(" host_tcq_wr = 0x%x host_tcq_rd = 0x%x \n", iadev->host_tcq_wr,
1040 printk("tcq_st_ptr = 0x%x tcq_ed_ptr = 0x%x \n", tcq_st_ptr, tcq_ed_ptr);
1041 i = 0;
1047 for(i=0; i <iadev->num_tx_desc; i++)
1056 #if 0 /* closing the receiving size will cause too many excp int */
1063 state = readl(iadev->reass_reg + STATE_REG) & 0xffff;
1066 excpq_rd_ptr = readw(iadev->reass_reg + EXCP_Q_RD_PTR) & 0xffff;
1072 error = readw(iadev->reass_ram+excpq_rd_ptr+2) & 0x0007;
1075 if (excpq_rd_ptr > (readw(iadev->reass_reg + EXCP_Q_ED_ADR)& 0xffff))
1076 excpq_rd_ptr = readw(iadev->reass_reg + EXCP_Q_ST_ADR)& 0xffff;
1078 state = readl(iadev->reass_reg + STATE_REG) & 0xffff;
1108 if (iadev->rfL.pcq_rd == (readw(iadev->reass_reg+PCQ_WR_PTR)&0xffff))
1114 desc = readw(iadev->reass_ram+iadev->rfL.pcq_rd) & 0x1fff;
1115 IF_RX(printk("reass_ram = %p iadev->rfL.pcq_rd = 0x%x desc = %d\n",
1117 printk(" pcq_wr_ptr = 0x%x\n",
1118 readw(iadev->reass_reg+PCQ_WR_PTR)&0xffff);)
1133 ((buf_desc_ptr->vc_index & 0xffff) >= iadev->num_vc)) {
1138 vcc = iadev->rx_open[buf_desc_ptr->vc_index & 0xffff];
1204 out: return 0;
1217 status = readl(iadev->reass_reg+REASS_INTR_STATUS_REG) & 0xffff;
1218 IF_EVENT(printk("rx_intr: status = 0x%x\n", status);)
1227 state = readl(iadev->reass_reg + STATE_REG) & 0xffff;
1232 state = readl(iadev->reass_reg + STATE_REG) & 0xffff;
1241 iadev->rxing = 0;
1244 ((iadev->rx_pkt_cnt - iadev->rx_tmp_cnt) == 0)) {
1303 printk("rx_dle_intr: skb len 0\n");
1364 state = readl(iadev->reass_reg + STATE_REG) & 0xffff;
1366 state = readl(iadev->reass_reg + REASS_MASK_REG) & 0xffff;
1382 if (vcc->qos.rxtp.traffic_class == ATM_NONE) return 0;
1404 ia_open_abr_vc(iadev, &srv_p, vcc, 0);
1416 return 0;
1423 unsigned long rx_pkt_start = 0;
1451 writel(iadev->rx_dle_dma & 0xfffff000,
1453 IF_INIT(printk("Tx Dle list addr: 0x%p value: 0x%0x\n",
1456 printk("Rx Dle list addr: 0x%p value: 0x%0x\n",
1460 writew(0xffff, iadev->reass_reg+REASS_MASK_REG);
1461 writew(0, iadev->reass_reg+MODE_REG);
1467 Buffer descr 0x0000 (736 - 23K)
1468 VP Table 0x5c00 (256 - 512)
1469 Except q 0x5e00 (128 - 512)
1470 Free buffer q 0x6000 (1K - 2K)
1471 Packet comp q 0x6800 (1K - 2K)
1472 Reass Table 0x7000 (1K - 2K)
1473 VC Table 0x7800 (1K - 2K)
1474 ABR VC Table 0x8000 (1K - 32K)
1485 memset_io(buf_desc_ptr, 0, sizeof(*buf_desc_ptr));
1490 memset_io(buf_desc_ptr, 0, sizeof(*buf_desc_ptr));
1492 buf_desc_ptr->buf_start_lo = rx_pkt_start & 0x0000ffff;
1496 IF_INIT(printk("Rx Buffer desc ptr: 0x%p\n", buf_desc_ptr);)
1513 IF_INIT(printk("freeq_start: 0x%p\n", freeq_start);)
1515 i = (PKT_COMP_Q * iadev->memSize) & 0xffff;
1522 i = (EXCEPTION_Q * iadev->memSize) & 0xffff;
1530 iadev->rfL.fdq_st = readw(iadev->reass_reg+FREEQ_ST_ADR) & 0xffff;
1531 iadev->rfL.fdq_ed = readw(iadev->reass_reg+FREEQ_ED_ADR) & 0xffff ;
1532 iadev->rfL.fdq_rd = readw(iadev->reass_reg+FREEQ_RD_PTR) & 0xffff;
1533 iadev->rfL.fdq_wr = readw(iadev->reass_reg+FREEQ_WR_PTR) & 0xffff;
1534 iadev->rfL.pcq_st = readw(iadev->reass_reg+PCQ_ST_ADR) & 0xffff;
1535 iadev->rfL.pcq_ed = readw(iadev->reass_reg+PCQ_ED_ADR) & 0xffff;
1536 iadev->rfL.pcq_rd = readw(iadev->reass_reg+PCQ_RD_PTR) & 0xffff;
1537 iadev->rfL.pcq_wr = readw(iadev->reass_reg+PCQ_WR_PTR) & 0xffff;
1539 IF_INIT(printk("INIT:pcq_st:0x%x pcq_ed:0x%x pcq_rd:0x%x pcq_wr:0x%x",
1544 /* writew(0x0b80, iadev->reass_reg+VP_LKUP_BASE); */
1546 - I guess we can write all 1s or 0x000f in the entire memory
1556 for(i=0; i < j; i++)
1559 vcsize_sel = 0;
1565 writew(((i>>3) & 0xfff8) | vcsize_sel, iadev->reass_reg+VC_LKUP_BASE);
1568 for(i = 0; i < j; i++)
1585 memset ((char*)abr_vc_table, 0, j * sizeof(*abr_vc_table));
1586 for(i = 0; i < j; i++) {
1587 abr_vc_table->rdf = 0x0003;
1588 abr_vc_table->air = 0x5eb1;
1595 writew(0xff00, iadev->reass_reg+VP_FILTER);
1596 writew(0, iadev->reass_reg+XTRA_RM_OFFSET);
1597 writew(0x1, iadev->reass_reg+PROTOCOL_ID);
1603 writew(0xF6F8, iadev->reass_reg+PKT_TM_CNT );
1605 i = (j >> 6) & 0xFF;
1607 i |= ((j << 2) & 0xFF00);
1611 for(i=0; i<iadev->num_tx_desc;i++)
1612 iadev->desc_tbl[i].timestamp = 0;
1631 iadev->rx_pkt_cnt = 0;
1634 return 0;
1648 Buffer descr 0x0000 (128 - 4K)
1649 UBR sched 0x1000 (1K - 4K)
1650 UBR Wait q 0x2000 (1K - 4K)
1651 Commn queues 0x3000 Packet Ready, Trasmit comp(0x3100)
1653 extended VC 0x4000 (1K - 8K)
1654 ABR sched 0x6000 and ABR wait queue (1K - 2K) each
1655 CBR sched 0x7000 (as needed)
1656 VC table 0x8000 (1K - 32K)
1727 if ((vcc->pop) && (skb->len != 0))
1739 IF_EVENT(printk("tx_dle_intr: enque skb = 0x%p \n", skb);)
1755 if (vcc->qos.txtp.traffic_class == ATM_NONE) return 0;
1769 memset((caddr_t)ia_vcc, 0, sizeof(*ia_vcc));
1778 ia_vcc->vc_desc_cnt = 0;
1784 else if ((vcc->qos.txtp.max_pcr == 0)&&( vcc->qos.txtp.pcr <= 0))
1786 else if ((vcc->qos.txtp.max_pcr > vcc->qos.txtp.pcr) && (vcc->qos.txtp.max_pcr> 0))
1801 if (vcc->qos.txtp.max_sdu != 0) {
1817 memset((caddr_t)vc, 0, sizeof(*vc));
1818 memset((caddr_t)evc, 0, sizeof(*evc));
1825 evc->atm_hdr1 = (vcc->vci >> 12) & 0x000f;
1826 evc->atm_hdr2 = (vcc->vci & 0x0fff) << 4;
1834 if (vcc->qos.txtp.pcr > 0)
1836 IF_UBR(printk("UBR: txtp.pcr = 0x%x f_rate = 0x%x\n",
1843 if (vcc->qos.txtp.pcr > 0)
1845 if (vcc->qos.txtp.min_pcr > 0) {
1852 else srv_p.mcr = 0;
1887 if ((ret = ia_cbr_setup (iadev, vcc)) < 0) {
1896 return 0;
1919 IF_INIT(printk("Tx MASK REG: 0x%0x\n",
1935 writel(iadev->tx_dle_dma & 0xfffff000,
1937 writew(0xffff, iadev->seg_reg+SEG_MASK_REG);
1938 writew(0, iadev->seg_reg+MODE_REG_0);
1947 Buffer descr 0x0000 (128 - 4K)
1948 Commn queues 0x1000 Transmit comp, Packet ready(0x1400)
1951 CBR Table 0x1800 (as needed) - 6K
1952 UBR Table 0x3000 (1K - 4K) - 12K
1953 UBR Wait queue 0x4000 (1K - 4K) - 16K
1954 ABR sched 0x5000 and ABR wait queue (1K - 2K) each
1956 extended VC 0x6000 (1K - 8K) - 24K
1957 VC Table 0x8000 (1K - 32K) - 32K
1959 Between 0x2000 (8K) and 0x3000 (12K) there is 4K space left for VBR Tbl
1968 memset((caddr_t)buf_desc_ptr, 0, sizeof(*buf_desc_ptr));
1973 memset((caddr_t)buf_desc_ptr, 0, sizeof(*buf_desc_ptr));
1976 buf_desc_ptr->buf_start_lo = tx_pkt_start & 0x0000ffff;
1987 for (i= 0; i< iadev->num_tx_desc; i++)
2039 iadev->ffL.prq_st = readw(iadev->seg_reg+PRQ_ST_ADR) & 0xffff;
2040 iadev->ffL.prq_ed = readw(iadev->seg_reg+PRQ_ED_ADR) & 0xffff;
2041 iadev->ffL.prq_wr = readw(iadev->seg_reg+PRQ_WR_PTR) & 0xffff;
2043 iadev->ffL.tcq_st = readw(iadev->seg_reg+TCQ_ST_ADR) & 0xffff;
2044 iadev->ffL.tcq_ed = readw(iadev->seg_reg+TCQ_ED_ADR) & 0xffff;
2045 iadev->ffL.tcq_rd = readw(iadev->seg_reg+TCQ_RD_PTR) & 0xffff;
2053 *prq_start = (u_short)0; /* desc 1 in all entries */
2058 #if 1 /* for 1K VC board, CBR_PTR_BASE is 0 */
2059 writew(0,iadev->seg_reg+CBR_PTR_BASE);
2062 IF_INIT(printk("cbr_ptr_base = 0x%x ", tmp16);)
2066 IF_INIT(printk("value in register = 0x%x\n",
2070 IF_INIT(printk("cbr_tab_beg = 0x%x in reg = 0x%x \n", tmp16,
2075 IF_INIT(printk("iadev->seg_reg = 0x%p CBR_PTR_BASE = 0x%x\n",
2077 IF_INIT(printk("CBR_TAB_BEG = 0x%x, CBR_TAB_END = 0x%x, CBR_PTR = 0x%x\n",
2083 0, iadev->num_vc*6);
2085 iadev->CbrEntryPt = 0;
2087 iadev->NumEnabledCBR = 0;
2090 /* initialize all bytes of UBR scheduler table and wait queue to 0
2098 vcsize_sel = 0;
2106 writew(vcsize_sel | ((i >> 8) & 0xfff8),iadev->seg_reg+VCT_BASE);
2108 writew((i >> 8) & 0xfffe, iadev->seg_reg+VCTE_BASE);
2110 writew((i & 0xffff) >> 11, iadev->seg_reg+UBR_SBPTR_BASE);
2112 writew((i >> 7) & 0xffff, iadev->seg_reg+UBRWQ_BASE);
2114 0, iadev->num_vc*8);
2115 /* ABR scheduling Table(0x5000-0x57ff) and wait queue(0x5800-0x5fff)*/
2116 /* initialize all bytes of ABR scheduler table and wait queue to 0
2124 writew((i >> 11) & 0xffff, iadev->seg_reg+ABR_SBPTR_BASE);
2126 writew((i >> 7) & 0xffff, iadev->seg_reg+ABRWQ_BASE);
2129 memset((caddr_t)(iadev->seg_ram+i), 0, iadev->num_vc*4);
2139 for(i=0; i<iadev->num_vc; i++)
2141 memset((caddr_t)vc, 0, sizeof(*vc));
2142 memset((caddr_t)evc, 0, sizeof(*evc));
2147 iadev->testTable[i]->lastTime = 0;
2148 iadev->testTable[i]->fract = 0;
2159 writew((UBR_EN | (0x23 << 2)), iadev->seg_reg+STPARMS);
2163 writew((UBR_EN | ABR_EN | (0x23 << 2)), iadev->seg_reg+STPARMS);
2166 writew(0, iadev->seg_reg+IDLEHEADHI);
2167 writew(0, iadev->seg_reg+IDLEHEADLO);
2170 writew(0xaa00, iadev->seg_reg+ABRUBR_ARB);
2172 iadev->close_pending = 0;
2185 /* Mode Register 0 */
2194 iadev->tx_pkt_cnt = 0;
2197 return 0;
2200 while (--i >= 0)
2208 while (--i >= 0) {
2228 int handled = 0;
2232 while( (status = readl(iadev->reg+IPHASE5575_BUS_STATUS_REG) & 0x7f))
2235 IF_EVENT(printk("ia_int: status = 0x%x\n", status);)
2282 IF_INIT(printk("ESI: 0x%08x%04x\n", mac1, mac2);)
2283 for (i=0; i<MAC1_LEN; i++)
2286 for (i=0; i<MAC2_LEN; i++)
2288 return 0;
2298 for(i=0; i<64; i++)
2302 writel(0, iadev->reg+IPHASE5575_EXT_RESET);
2303 for(i=0; i<64; i++)
2308 return 0;
2325 dev->ci_range.vpi_bits = 0;
2329 real_base = pci_resource_start (iadev->pci, 0);
2334 printk(KERN_ERR DEV_LABEL "(itf %d): init error 0x%x\n",
2338 IF_INIT(printk(DEV_LABEL "(itf %d): rev.%d,realbase=0x%lx,irq=%d\n",
2343 iadev->pci_map_size = pci_resource_len(iadev->pci, 0);
2345 if (iadev->pci_map_size == 0x100000){
2350 else if (iadev->pci_map_size == 0x40000) {
2355 printk("Unknown pci_map_size = 0x%x\n", iadev->pci_map_size);
2412 for (i=0; i < ESI_LEN; i++)
2422 return 0;
2428 iadev->rx_cell_cnt += readw(iadev->reass_reg+CELL_CTR0)&0xffff;
2429 iadev->rx_cell_cnt += (readw(iadev->reass_reg+CELL_CTR1) & 0xffff) << 16;
2430 iadev->drop_rxpkt += readw(iadev->reass_reg + DRP_PKT_CNTR ) & 0xffff;
2431 iadev->drop_rxcell += readw(iadev->reass_reg + ERR_CNTR) & 0xffff;
2432 iadev->tx_cell_cnt += readw(iadev->seg_reg + CELL_CTR_LO_AUTO)&0xffff;
2433 iadev->tx_cell_cnt += (readw(iadev->seg_reg+CELL_CTR_HIGH_AUTO)&0xffff)<<16;
2439 static u_char blinking[8] = {0, 0, 0, 0, 0, 0, 0, 0};
2442 for (i = 0; i < iadev_count; i++) {
2445 if (blinking[i] == 0) {
2452 blinking[i] = 0;
2483 for (i = 0; i < iadev->num_vc; i++)
2486 for (i = 0; i < iadev->num_tx_desc; i++) {
2526 "master (0x%x)\n",dev->number, error);
2572 phy = 0; /* resolve compiler complaint */
2574 if ((phy=ia_phy_get(dev,0)) == 0x30)
2575 printk("IA: pm5346,rev.%d\n",phy&0x0f);
2577 printk("IA: utopia,rev.%0x\n",phy);)
2595 return 0;
2644 if (closetime == 0)
2647 wait_event_timeout(iadev->close_wait, (ia_vcc->vc_desc_cnt <= 0), closetime);
2650 iadev->testTable[vcc->vci]->lastTime = 0;
2651 iadev->testTable[vcc->vci]->fract = 0;
2654 if (vcc->qos.txtp.min_pcr > 0)
2678 abr_vc_table->rdf = 0x0003;
2679 abr_vc_table->air = 0x5eb1;
2732 #if 0
2738 first = 0;
2743 return 0;
2749 return 0;
2766 if ((board < 0) || (board > iadev_count))
2767 board = 0;
2778 for(i=0; i<0x80; i+=2, tmps++)
2779 if(put_user((u16)(readl(iadev->seg_reg+i) & 0xffff), tmps)) return -EFAULT;
2780 ia_cmds.status = 0;
2781 ia_cmds.len = 0x80;
2786 for(i=0; i<0x80; i+=2, tmps++)
2787 if(put_user((u16)(readl(iadev->reass_reg+i) & 0xffff), tmps)) return -EFAULT;
2788 ia_cmds.status = 0;
2789 ia_cmds.len = 0x80;
2803 for (i=0; i<(sizeof (rfredn_t))/4; i++)
2804 ((u_int *)rfL)[i] = readl(iadev->reass_reg + i) & 0xffff;
2806 for (i=0; i<(sizeof (ffredn_t))/4; i++)
2807 ((u_int *)ffL)[i] = readl(iadev->seg_reg + i) & 0xffff;
2815 ia_cmds.status = 0;
2822 ia_cmds.status = 0;
2825 case 0x6:
2827 ia_cmds.status = 0;
2828 printk("skb = 0x%p\n", skb_peek(&iadev->tx_backlog));
2829 printk("rtn_q: 0x%p\n",ia_deque_rtn_q(&iadev->tx_return_q));
2832 case 0x8:
2846 ia_cmds.status = 0;
2848 case 0x9:
2856 ia_cmds.status = 0;
2859 case 0xb:
2863 case 0xa:
2866 ia_cmds.status = 0;
2872 ia_cmds.status = 0;
2881 return 0;
2902 return 0;
2911 return 0;
2919 return 0;
2927 if (desc == 0xffff)
2930 desc &= 0x1fff;
2932 if ((desc == 0) || (desc > iadev->num_tx_desc))
2940 return 0; /* return SUCCESS */
2953 IA_SKB_STATE(skb) = 0;
2977 IF_TX(printk("Sent: skb = 0x%p skb->data: 0x%p len: %d, desc: %d\n",
2979 trailer->control = 0;
2981 trailer->length = ((skb->len & 0xff) << 8) | ((skb->len & 0xff00) >> 8);
2982 trailer->crc32 = 0; /* not needed - dummy bytes */
3004 memset((caddr_t)wr_ptr, 0, sizeof(*wr_ptr));
3012 /* hw bug - DLEs of 0x2d, 0x2e, 0x2f cause DMA lockup */
3013 if ((wr_ptr->bytes >> 2) == 0xb)
3014 wr_ptr->bytes = 0x30;
3017 wr_ptr->prq_wr_ptr_data = 0;
3045 #if 0
3047 if (atomic_read(&vcc->stats->tx) % 20 == 0) {
3053 } else if ((iavcc->flow_inc < 0) && (iavcc->vc_desc_cnt < 3)) {
3056 iavcc->flow_inc = 0;
3061 return 0;
3094 return 0;
3117 if (iadev->pci_map_size == 0x40000)
3147 return 0;
3189 IF_INIT(printk("dev_id = 0x%p iadev->LineRate = %d \n", dev,
3210 return 0;
3253 { PCI_VENDOR_ID_IPHASE, 0x0008, PCI_ANY_ID, PCI_ANY_ID, },
3254 { PCI_VENDOR_ID_IPHASE, 0x0009, PCI_ANY_ID, PCI_ANY_ID, },
3255 { 0,}
3271 if (ret >= 0) {