637 static int mv_stop_edma_engine(void __iomem *port_mmio);
948 	void __iomem *port_mmio = mv_ap_base(ap);  in mv_save_cached_regs()  local
951 	pp->cached.fiscfg = readl(port_mmio + FISCFG);  in mv_save_cached_regs()
952 	pp->cached.ltmode = readl(port_mmio + LTMODE);  in mv_save_cached_regs()
953 	pp->cached.haltcond = readl(port_mmio + EDMA_HALTCOND);  in mv_save_cached_regs()
954 	pp->cached.unknown_rsvd = readl(port_mmio + EDMA_UNKNOWN_RSVD);  in mv_save_cached_regs()
992 static void mv_set_edma_ptrs(void __iomem *port_mmio,  in mv_set_edma_ptrs()  argument
1005 	writel((pp->crqb_dma >> 16) >> 16, port_mmio + EDMA_REQ_Q_BASE_HI);  in mv_set_edma_ptrs()
1007 		 port_mmio + EDMA_REQ_Q_IN_PTR);  in mv_set_edma_ptrs()
1008 	writelfl(index, port_mmio + EDMA_REQ_Q_OUT_PTR);  in mv_set_edma_ptrs()
1017 	writel((pp->crpb_dma >> 16) >> 16, port_mmio + EDMA_RSP_Q_BASE_HI);  in mv_set_edma_ptrs()
1018 	writelfl(index, port_mmio + EDMA_RSP_Q_IN_PTR);  in mv_set_edma_ptrs()
1020 		 port_mmio + EDMA_RSP_Q_OUT_PTR);  in mv_set_edma_ptrs()
1068 					  void __iomem *port_mmio,  in mv_clear_and_enable_port_irqs()  argument
1078 	writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE);  in mv_clear_and_enable_port_irqs()
1086 		writelfl(0, port_mmio + FIS_IRQ_CAUSE);  in mv_clear_and_enable_port_irqs()
1163 static void mv_start_edma(struct ata_port *ap, void __iomem *port_mmio,  in mv_start_edma()  argument
1178 		mv_set_edma_ptrs(port_mmio, hpriv, pp);  in mv_start_edma()
1179 		mv_clear_and_enable_port_irqs(ap, port_mmio, DONE_IRQ|ERR_IRQ);  in mv_start_edma()
1181 		writelfl(EDMA_EN, port_mmio + EDMA_CMD);  in mv_start_edma()
1188 	void __iomem *port_mmio = mv_ap_base(ap);  in mv_wait_for_edma_empty_idle()  local
1201 		u32 edma_stat = readl(port_mmio + EDMA_STATUS);  in mv_wait_for_edma_empty_idle()
1216 static int mv_stop_edma_engine(void __iomem *port_mmio)  in mv_stop_edma_engine()  argument
1221 	writelfl(EDMA_DS, port_mmio + EDMA_CMD);  in mv_stop_edma_engine()
1225 		u32 reg = readl(port_mmio + EDMA_CMD);  in mv_stop_edma_engine()
1235 	void __iomem *port_mmio = mv_ap_base(ap);  in mv_stop_edma()  local
1243 	if (mv_stop_edma_engine(port_mmio)) {  in mv_stop_edma()
1477 	void __iomem *port_mmio;  in mv_config_fbs()  local
1497 	port_mmio = mv_ap_base(ap);  in mv_config_fbs()
1498 	mv_write_cached_reg(port_mmio + FISCFG, old_fiscfg, fiscfg);  in mv_config_fbs()
1499 	mv_write_cached_reg(port_mmio + LTMODE, old_ltmode, ltmode);  in mv_config_fbs()
1500 	mv_write_cached_reg(port_mmio + EDMA_HALTCOND, old_haltcond, haltcond);  in mv_config_fbs()
1602 	void __iomem *port_mmio    = mv_ap_base(ap);  in mv_edma_cfg()  local
1658 	writelfl(cfg, port_mmio + EDMA_CFG);  in mv_edma_cfg()
1880 	void __iomem *port_mmio = mv_ap_base(ap);  in mv_bmdma_setup()  local
1886 	writel(0, port_mmio + BMDMA_CMD);  in mv_bmdma_setup()
1890 		port_mmio + BMDMA_PRD_HIGH);  in mv_bmdma_setup()
1892 		port_mmio + BMDMA_PRD_LOW);  in mv_bmdma_setup()
1908 	void __iomem *port_mmio = mv_ap_base(ap);  in mv_bmdma_start()  local
1913 	writelfl(cmd, port_mmio + BMDMA_CMD);  in mv_bmdma_start()
1927 	void __iomem *port_mmio = mv_ap_base(ap);  in mv_bmdma_stop_ap()  local
1931 	cmd = readl(port_mmio + BMDMA_CMD);  in mv_bmdma_stop_ap()
1934 		writelfl(cmd, port_mmio + BMDMA_CMD);  in mv_bmdma_stop_ap()
1957 	void __iomem *port_mmio = mv_ap_base(ap);  in mv_bmdma_status()  local
1964 	reg = readl(port_mmio + BMDMA_STATUS);  in mv_bmdma_status()
2226 	void __iomem *port_mmio = mv_ap_base(ap);  in mv_send_fis()  local
2231 	old_ifctl = readl(port_mmio + SATA_IFCTL);  in mv_send_fis()
2233 	writelfl(ifctl, port_mmio + SATA_IFCTL);  in mv_send_fis()
2237 		writel(fis[i], port_mmio + VENDOR_UNIQUE_FIS);  in mv_send_fis()
2240 	writelfl(ifctl | 0x200, port_mmio + SATA_IFCTL);  in mv_send_fis()
2241 	writelfl(fis[final_word], port_mmio + VENDOR_UNIQUE_FIS);  in mv_send_fis()
2248 		ifstat = readl(port_mmio + SATA_IFSTAT);  in mv_send_fis()
2252 	writelfl(old_ifctl, port_mmio + SATA_IFCTL);  in mv_send_fis()
2333 	void __iomem *port_mmio = mv_ap_base(ap);  in mv_qc_issue()  local
2349 		mv_start_edma(ap, port_mmio, pp, qc->tf.protocol);  in mv_qc_issue()
2355 					port_mmio + EDMA_REQ_Q_IN_PTR);  in mv_qc_issue()
2460 	void __iomem *port_mmio = mv_ap_base(ap);  in mv_get_err_pmp_map()  local
2462 	return readl(port_mmio + SATA_TESTCTL) >> 16;  in mv_get_err_pmp_map()
2490 	void __iomem *port_mmio = mv_ap_base(ap);  in mv_req_q_empty()  local
2493 	in_ptr  = (readl(port_mmio + EDMA_REQ_Q_IN_PTR)  in mv_req_q_empty()
2495 	out_ptr = (readl(port_mmio + EDMA_REQ_Q_OUT_PTR)  in mv_req_q_empty()
2635 	void __iomem *port_mmio = mv_ap_base(ap);  in mv_err_intr()  local
2653 	edma_err_cause = readl(port_mmio + EDMA_ERR_IRQ_CAUSE);  in mv_err_intr()
2655 		fis_cause = readl(port_mmio + FIS_IRQ_CAUSE);  in mv_err_intr()
2656 		writelfl(~fis_cause, port_mmio + FIS_IRQ_CAUSE);  in mv_err_intr()
2658 	writelfl(~edma_err_cause, port_mmio + EDMA_ERR_IRQ_CAUSE);  in mv_err_intr()
2798 	void __iomem *port_mmio = mv_ap_base(ap);  in mv_process_crpb_entries()  local
2806 	in_index = (readl(port_mmio + EDMA_RSP_Q_IN_PTR)  in mv_process_crpb_entries()
2834 			 port_mmio + EDMA_RSP_Q_OUT_PTR);  in mv_process_crpb_entries()
3154 #define ZERO(reg) writel(0, port_mmio + (reg))
3158 	void __iomem *port_mmio = mv_port_base(mmio, port);  in mv5_reset_hc_port()  local
3163 	writel(0x11f, port_mmio + EDMA_CFG);  in mv5_reset_hc_port()
3174 	writel(0xbc, port_mmio + EDMA_IORDY_TMOUT);  in mv5_reset_hc_port()
3317 	void __iomem *port_mmio;  in mv6_read_preamp()  local
3327 	port_mmio = mv_port_base(mmio, idx);  in mv6_read_preamp()
3328 	tmp = readl(port_mmio + PHY_MODE2);  in mv6_read_preamp()
3342 	void __iomem *port_mmio = mv_port_base(mmio, port);  in mv6_phy_errata()  local
3352 		m2 = readl(port_mmio + PHY_MODE2);  in mv6_phy_errata()
3355 		writel(m2, port_mmio + PHY_MODE2);  in mv6_phy_errata()
3359 		m2 = readl(port_mmio + PHY_MODE2);  in mv6_phy_errata()
3361 		writel(m2, port_mmio + PHY_MODE2);  in mv6_phy_errata()
3370 	m3 = readl(port_mmio + PHY_MODE3);  in mv6_phy_errata()
3378 		u32 m4 = readl(port_mmio + PHY_MODE4);  in mv6_phy_errata()
3388 		writel(m4, port_mmio + PHY_MODE4);  in mv6_phy_errata()
3396 	writel(m3, port_mmio + PHY_MODE3);  in mv6_phy_errata()
3399 	m2 = readl(port_mmio + PHY_MODE2);  in mv6_phy_errata()
3412 	writel(m2, port_mmio + PHY_MODE2);  in mv6_phy_errata()
3426 	void __iomem *port_mmio;  in mv_soc_read_preamp()  local
3429 	port_mmio = mv_port_base(mmio, idx);  in mv_soc_read_preamp()
3430 	tmp = readl(port_mmio + PHY_MODE2);  in mv_soc_read_preamp()
3437 #define ZERO(reg) writel(0, port_mmio + (reg))
3441 	void __iomem *port_mmio = mv_port_base(mmio, port);  in mv_soc_reset_hc_port()  local
3446 	writel(0x101f, port_mmio + EDMA_CFG);  in mv_soc_reset_hc_port()
3457 	writel(0x800, port_mmio + EDMA_IORDY_TMOUT);  in mv_soc_reset_hc_port()
3504 	void __iomem *port_mmio = mv_port_base(mmio, port);  in mv_soc_65n_phy_errata()  local
3507 	reg = readl(port_mmio + PHY_MODE3);  in mv_soc_65n_phy_errata()
3512 	writel(reg, port_mmio + PHY_MODE3);  in mv_soc_65n_phy_errata()
3514 	reg = readl(port_mmio + PHY_MODE4);  in mv_soc_65n_phy_errata()
3517 	writel(reg, port_mmio + PHY_MODE4);  in mv_soc_65n_phy_errata()
3519 	reg = readl(port_mmio + PHY_MODE9_GEN2);  in mv_soc_65n_phy_errata()
3523 	writel(reg, port_mmio + PHY_MODE9_GEN2);  in mv_soc_65n_phy_errata()
3525 	reg = readl(port_mmio + PHY_MODE9_GEN1);  in mv_soc_65n_phy_errata()
3529 	writel(reg, port_mmio + PHY_MODE9_GEN1);  in mv_soc_65n_phy_errata()
3548 static void mv_setup_ifcfg(void __iomem *port_mmio, int want_gen2i)  in mv_setup_ifcfg()  argument
3550 	u32 ifcfg = readl(port_mmio + SATA_IFCFG);  in mv_setup_ifcfg()
3555 	writelfl(ifcfg, port_mmio + SATA_IFCFG);  in mv_setup_ifcfg()
3561 	void __iomem *port_mmio = mv_port_base(mmio, port_no);  in mv_reset_channel()  local
3568 	mv_stop_edma_engine(port_mmio);  in mv_reset_channel()
3569 	writelfl(EDMA_RESET, port_mmio + EDMA_CMD);  in mv_reset_channel()
3573 		mv_setup_ifcfg(port_mmio, 1);  in mv_reset_channel()
3580 	writelfl(EDMA_RESET, port_mmio + EDMA_CMD);  in mv_reset_channel()
3582 	writelfl(0, port_mmio + EDMA_CMD);  in mv_reset_channel()
3593 		void __iomem *port_mmio = mv_ap_base(ap);  in mv_pmp_select()  local
3594 		u32 reg = readl(port_mmio + SATA_IFCTL);  in mv_pmp_select()
3599 			writelfl(reg, port_mmio + SATA_IFCTL);  in mv_pmp_select()
3670 	void __iomem *port_mmio = mv_ap_base(ap);  in mv_eh_thaw()  local
3674 	writel(0, port_mmio + EDMA_ERR_IRQ_CAUSE);  in mv_eh_thaw()
3695 static void mv_port_init(struct ata_ioports *port,  void __iomem *port_mmio)  in mv_port_init()  argument
3697 	void __iomem *serr, *shd_base = port_mmio + SHD_BLK;  in mv_port_init()
3715 	serr = port_mmio + mv_scr_offset(SCR_ERROR);  in mv_port_init()
3717 	writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE);  in mv_port_init()
3720 	writelfl(~EDMA_ERR_IRQ_TRANSIENT, port_mmio + EDMA_ERR_IRQ_MASK);  in mv_port_init()
3957 		void __iomem *port_mmio = mv_port_base(mmio, port);  in mv_init_host()  local
3959 		mv_port_init(&ap->ioaddr, port_mmio);  in mv_init_host()
4413 		void __iomem *port_mmio = mv_port_base(hpriv->base, port);  in mv_pci_init_one()  local
4414 		unsigned int offset = port_mmio - hpriv->base;  in mv_pci_init_one()